Update Bender.lock, Bender.yml, Xilinx constraints, memory size.

pulp-platform · May 11, 2024 · a1bf3b5 · a1bf3b5
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Showing 6 changed files with 74 additions and 32 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -41,8 +41,8 @@ packages:
     - apb
     - common_cells
   axi:
-    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
-    version: 0.39.2
+    revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
+    version: 0.39.3
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -71,14 +71,26 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cv32e40x:
-    revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8
+    revision: null
+    version: null
     source:
-      Git: https://github.com/pulp-platform/cv32e40x.git
+      Path: working_dir/cv32e40x
     dependencies: []
+  fir-hwpe:
+    revision: null
+    version: null
+    source:
+      Path: working_dir/fir-hwpe
+    dependencies:
+    - hci
+    - hwpe-ctrl
+    - hwpe-stream
+    - zeroriscy
   fir-xifu:
-    revision: 0fbc043db0798adbb3bec8ee37b7b08f010cce23
+    revision: null
+    version: null
     source:
-      Git: https://iis-git.ee.ethz.ch/ades-labs/fir-xifu.git
+      Path: working_dir/fir-xifu
     dependencies:
     - cv32e40x
   fpnew:
@@ -114,26 +126,27 @@ packages:
     - common_verification
     - register_interface
     - tech_cells_generic
-  hwpe-ctrl:
-    revision: 1916c72f024175f1fe351acc3db3c6e9925a117d
-    version: 1.7.3
+  hci:
+    revision: null
+    version: null
     source:
-      Git: https://github.com/pulp-platform/hwpe-ctrl.git
+      Path: working_dir/hci
     dependencies:
-    - tech_cells_generic
-  hwpe-mac-engine:
-    revision: cd48c574f1972ecbe02d3f463a0e12a92acde484
-    version: 1.3.3
+    - cluster_interconnect
+    - hwpe-stream
+    - l2_tcdm_hybrid_interco
+  hwpe-ctrl:
+    revision: 877d676329785f7bba042402e0a6f329a387573d
+    version: null
     source:
-      Git: https://github.com/pulp-platform/hwpe-mac-engine.git
+      Git: git@github.com:pulp-platform/hwpe-ctrl.git
     dependencies:
-    - hwpe-ctrl
-    - hwpe-stream
+    - tech_cells_generic
   hwpe-stream:
     revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1
     version: 1.8.0
     source:
-      Git: https://github.com/pulp-platform/hwpe-stream.git
+      Git: git@github.com:pulp-platform/hwpe-stream.git
     dependencies:
     - tech_cells_generic
   ibex:
@@ -149,6 +162,12 @@ packages:
     source:
       Git: https://github.com/pulp-platform/jtag_pulp.git
     dependencies: []
+  l2_tcdm_hybrid_interco:
+    revision: fa55e72859dcfb117a2788a77352193bef94ff2b
+    version: 1.0.0
+    source:
+      Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
+    dependencies: []
   pulp_io:
     revision: bee24f34798c8fd5c3c999726e90585bb0f4d65f
     version: null
@@ -167,9 +186,10 @@ packages:
     - udma_sdio
     - udma_uart
   pulp_soc:
-    revision: cc4d812dd2211e9f1602080c3ee788e4cd517ca5
+    revision: null
+    version: null
     source:
-      Git: https://github.com/pulp-platform/pulpissimo.git
+      Path: working_dir/pulp_soc
     dependencies:
     - adv_dbg_if
     - apb
@@ -181,10 +201,10 @@ packages:
     - cluster_interconnect
     - common_cells
     - cv32e40x
+    - fir-hwpe
     - fir-xifu
     - fpnew
     - generic_fll
-    - hwpe-mac-engine
     - ibex
     - jtag_pulp
     - pulp_io
@@ -337,3 +357,9 @@ packages:
     dependencies:
     - common_cells
     - udma_core
+  zeroriscy:
+    revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36
+    version: null
+    source:
+      Git: [email protected]:yvantor/ibex.git
+    dependencies: []
diff --git a/Bender.yml b/Bender.yml
@@ -16,7 +16,7 @@ dependencies:
   common_cells:                { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.21.0 }
   apb:                         { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4 }
   jtag_pulp:                   { git: "https://github.com/pulp-platform/jtag_pulp.git",          version: 0.2.0 }
-  pulp_soc:                    { git: "https://github.com/pulp-platform/pulp_soc.git",           rev: 645988c8533b5ff843699068d7c369e41ccec1d3 }
+  pulp_soc:                    { git: "https://github.com/pulp-platform/pulp_soc.git",           rev: "e507a97ab1e6e6c55d9c381418b2975cc0c62138" } # branch fc/cv32e40x
   tbtools:                     { git: "https://github.com/pulp-platform/tbtools.git",            version: 0.2.1 }
   tech_cells_generic:          { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
   pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" }

diff --git a/hw/pulpissimo.sv b/hw/pulpissimo.sv
@@ -39,7 +39,7 @@ module pulpissimo #(
   /// Standard RISC-V extension: Reuses the integer regfile for FPU usage instead of requiring a
   /// dedicated FPU regfile. Requires correct compiler settings for software to work!
   parameter  bit          USE_ZFINX = 1,
-  parameter  bit          USE_HWPE = 0,
+  parameter  bit          USE_HWPE = 1,
   /// Enable the virtual stdout interface for communication with simulated testbenches. This
   /// parameter must be disabled during any form of physical implementation.
   parameter  bit          SIM_STDOUT = 0,

diff --git a/target/fpga/Makefile b/target/fpga/Makefile
@@ -119,3 +119,16 @@ clean_zcu102:
 	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102 clean
 	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bit
 	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bin
+
+## Generates the bistream for the zyboz7 board
+zyboz7: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl
+	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 all
+	cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit
+	cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin
+	@echo "Bitstream generation for zyboz7 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zyboz7.bit and ./pulpissimo_zyboz7.bin"
+
+## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zyboz7 board.
+clean_zyboz7:
+	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 clean
+	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit
+	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin
diff --git a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc
@@ -19,6 +19,9 @@ create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_j
 set_input_jitter tck 1.000
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O]
 
+# generated clocks
+create_generated_clock -source [get_ports ref_clk_i] [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_in1]
+create_generated_clock -source [get_ports ref_clk_i] [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_in1]
 
 # minimize routing delay
 set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
@@ -30,9 +33,9 @@ set_max_delay -from [get_ports pad_jtag_tms] 20.000
 set_max_delay -from [get_ports pad_jtag_tdi] 20.000
 
 set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
-
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C]   -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D]   20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C]    -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D]    20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/jtag_tap_top_i/confreg/reg_bit_last/r_dataout_reg/C]     -to [get_pins i_pulpissimo/i_clock_gen/i_slow_clk_bypass_mux/i_BUFGMUX/I1]                                  20.000
 
 # reset signal
 set_false_path -from [get_ports pad_reset]
@@ -64,6 +67,9 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# waive DRCs related to emulated clock gating cells
+create_waiver -of_objects [get_methodology_violations -name xilinx_pulpissimo_methodology_drc_routed.rpx {TIMING-14#1}] -user fconti -description {emulated clock gating cells}
+
 #############################################################
 #  _____ ____         _____      _   _   _                  #
 # |_   _/ __ \       / ____|    | | | | (_)                 #

diff --git a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v
@@ -79,8 +79,8 @@ module xilinx_pulpissimo (
 );
 
   localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  localparam USE_FPU   = 1;
-  localparam USE_HWPE  = 0;
+  localparam USE_FPU   = 0;
+  localparam USE_HWPE  = 1;
 
   wire ref_clk_int;
   wire rst_n;
@@ -152,10 +152,7 @@ module xilinx_pulpissimo (
       pad_uart_cts,   // io_02
       pad_uart_rx,    // io_01
       pad_uart_tx     // io_00
-    } ),
-    .test_clk_o (test_clk_o),
-    .obs1_o (obs1_o),
-    .obs2_o (obs2_o)
+    } )
   );
 
 endmodule