Update padframe target

.gitignore

@@ -3,9 +3,10 @@ xcelium.d/
 xrun.history
 xrun.log
 .bender
-bender
+/utils/bin/bender
 work/
 compile.tcl
 working_dir/
-/padrick
+/utils/bin/padrick
 /Bender.local
+/build

Makefile

@@ -31,9 +31,12 @@ include $(PULPISSIMO_ROOT)/utils/utils.mk
 checkout: $(PULPISSIMO_UTILS)/bender
 	$(PULPISSIMO_UTILS)/bender checkout
 
-.PHONY: hw
+.PHONY: hw bootrom padframe
 ## Re-generate generated hardware IPs
-hw: hw/asic_autogen_rom.sv hw/fpga_autogen_rom.sv
+hw: bootrom padframe
+
+## Generate the boot rom
+bootrom: hw/asic_autogen_rom.sv hw/fpga_autogen_rom.sv
 
 ## Generate the ASIC and simulation boot rom
 hw/asic_autogen_rom.sv:
@@ -44,6 +47,21 @@ hw/asic_autogen_rom.sv:
 hw/fpga_autogen_rom.sv:
 	$(MAKE) -C sw/bootcode fpga_autogen_rom.sv
 	cp sw/bootcode/fpga_autogen_rom.sv $@
+
+padframe: hw/padframe/pulpissimo_padframe_rtl_sim_autogen hw/padframe/pulpissimo_padframe_fpga_autogen
+
+hw/padframe/pulpissimo_padframe_rtl_sim_autogen: $(PULPISSIMO_UTILS)/padrick
+	cd hw/padframe && $(PULPISSIMO_UTILS)/padrick generate -s padrick_generator_settings.yml rtl rtl_sim_padframe_config_top.yml -o pulpissimo_padframe_rtl_sim_autogen
+
+hw/padframe/pulpissimo_padframe_fpga_autogen: $(PULPISSIMO_UTILS)/padrick
+	cd hw/padframe && $(PULPISSIMO_UTILS)/padrick generate -s padrick_generator_settings.yml rtl fpga_padframe_config_top.yml -o pulpissimo_padframe_fpga_autogen
+
+.PHONY: gpio-reconfigure
+## Reconfigure number of GPIOs
+## @param GPIO=32 Number of GPIOs to reconfigure
+gpio-reconfigure:
+	$(MAKE) -C hw/vendored_ips/gpio reconfigure
+
 HELP_TITLE="PULPissimo Build & SIM Environment"
 HELP_DESCRIPTION="Toplevel targets for building and simulating PULPissimo. Please check the make files in the subdirectories for additional targets.."
 include $(PULPISSIMO_ROOT)/utils/help.mk

hw/clock_gen_fpga.sv

@@ -42,7 +42,7 @@ module clock_gen #(
 
   // Configuration interface for clock generation
   input logic  cfg_clk_i,
-               APB.Slave cfg_bus_slave,
+  APB.Slave    cfg_bus_slave,
 
 
   // Output clocks
@@ -73,9 +73,9 @@ module clock_gen #(
   logic        s_slow_clk_ungated;
 
   // Tie-off APB port with error response
-  cfg_bus_slave.pready  = 1'b1;
-  cfg_bus_slave.prdata  = 32'deadda7a;
-  cfg_bus_slave.pslverr = 1'b1;
+  assign cfg_bus_slave.pready  = 1'b1;
+  assign cfg_bus_slave.prdata  = 32'hdeadda7a;
+  assign cfg_bus_slave.pslverr = 1'b1;
 
   // Instantiate LogiCore clocking mngr IP
   xilinx_clk_mngr i_clk_manager (
@@ -127,7 +127,7 @@ module clock_gen #(
 
   // Instantiate clock divider to divide 8.3886 MHz PLL clock down to 32 kHz
   clk_int_div #(
-    .DIV_VALUE_WIDTH       ( 9    )
+    .DIV_VALUE_WIDTH       ( 9    ),
     .DEFAULT_DIV_VALUE     ( 256  ),
     .ENABLE_CLOCK_IN_RESET ( 1'b1 )
   ) i_slow_clk_div (

hw/padframe/custom_templates/rtl_templates/Bender.yml.mako

@@ -23,7 +23,7 @@ package:
     - "Padrick"
 
 dependencies:
-  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
+  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
 
 export_include_dirs:

hw/padframe/padframe_adapter.sv

@@ -21,9 +21,8 @@
 //-----------------------------------------------------------------------------
 
 module padframe_adapter #(
-  localparam NGPIO = gpio_reg_pkg::GPIOCount  // Have a look at the README in
-                                              // the GPIO repo in order to
-                                              // change the number of GPIOs.
+  /// Have a look at the README in the GPIO repo in order to change the number of GPIOs.
+  localparam int unsigned NGPIO = gpio_reg_pkg::GPIOCount
 )(
   input logic              soc_clk_i,
   input logic              soc_rstn_synced_i,

hw/padframe/pulpissimo_padframe_rtl_sim_autogen/Bender.yml

@@ -6,7 +6,7 @@ package:
     - "Padrick"
 
 dependencies:
-  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
+  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
 
 export_include_dirs:

hw/pulpissimo.sv

@@ -28,25 +28,23 @@
 // -----------------------------------------------------------------------------
 
 module pulpissimo #(
-  parameter  CORE_TYPE = 0, // 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  parameter  USE_XPULP = 1, // Enable XPULP extensions on CV32E40P. Has no
-                            // effect if an IBEX core variant is use.
-  parameter  USE_FPU = 1, // Mutually exclusive with the use of IBEX. I.e.
-                               // if an IBEX core variant is used, this paraeter
-                               // is ignored.
-  parameter  USE_ZFINX = 1, // Standard RISC-V extension: Reuses the integer
-                               // regfile for FPU usage instead of requiring a
-                               // dedicated FPU regfile. Requires correct
-                               // compiler settings for software to work!
-  parameter  USE_HWPE = 0,
-  parameter  SIM_STDOUT = 0, // Enable the virtual stdout interface for
-                               // communication with simulated testbenches. This
-                               // parameter must be disabled during any form of
-                               // physical implementation.
-  localparam IO_PAD_COUNT = gpio_reg_pkg::GPIOCount // The number of GPIO pads
-                                                    // in the system. Check the
-                                                    // README on how to modify
-                                                    // the pad count
+  /// 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY),
+  /// 2 for IBEX RV32EC (formerly MICRORISCY)
+  parameter  int unsigned CORE_TYPE = 0,
+  /// Enable XPULP extensions on CV32E40P. Has no effect if an IBEX core variant is use.
+  parameter  bit          USE_XPULP = 1,
+  /// Mutually exclusive with the use of IBEX. I.e. if an IBEX core variant is used, this parameter
+  /// is ignored.
+  parameter  bit          USE_FPU = 1,
+  /// Standard RISC-V extension: Reuses the integer regfile for FPU usage instead of requiring a
+  /// dedicated FPU regfile. Requires correct compiler settings for software to work!
+  parameter  bit          USE_ZFINX = 1,
+  parameter  bit          USE_HWPE = 0,
+  /// Enable the virtual stdout interface for communication with simulated testbenches. This
+  /// parameter must be disabled during any form of physical implementation.
+  parameter  bit          SIM_STDOUT = 0,
+  /// The number of GPIO pads in the system. Check the README on how to modify the pad count
+  localparam int unsigned IO_PAD_COUNT = gpio_reg_pkg::GPIOCount
 )(
   // Some platforms (e.g. Verilator) require to feed the clock externally. With
   // the EXTERNAL_CLOCK define we remove all internall clock generation logic.

utils/utils.mk

@@ -32,13 +32,13 @@ include $(mkfile_dir)/venv.mk
 $(PULPISSIMO_UTILS)/padrick:
 ifeq (,$(widlcard bin/padrick))
 	mkdir -p $(PULPISSIMO_UTILS)
-	cd $(PULPISSIMO_UTILS) && curl https://api.github.com/repos/pulp-platform/padrick/releases/tags/v0.3.4 \
+	cd $(PULPISSIMO_UTILS) && curl https://api.github.com/repos/pulp-platform/padrick/releases/tags/v0.3.6 \
     | grep "browser_download_url.*Padrick-x86_64.AppImage" \
     | cut -d : -f 2,3 \
     | tr -d \" \
     | wget -qi -
 	mv $(PULPISSIMO_UTILS)/Padrick-x86_64.AppImage $(PULPISSIMO_UTILS)/padrick
-	chmod a+x bin/padrick
+	chmod a+x $(PULPISSIMO_UTILS)/padrick
 endif
 
 $(PULPISSIMO_UTILS)/bender: