Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

All the things #384

Open
wants to merge 54 commits into
base: master
Choose a base branch
from
Open

All the things #384

wants to merge 54 commits into from

Conversation

stefanct
Copy link

I have no idea why I did no PR of these in the past. Probably because Pulpino is completely dead, but I'll do it now so that people might find it more easily. It contains mainly bug fixes and enhancements of the build infrastructure.

Rename messages.tcl to common.tcl and add a number of CPU
detection based on the system's getconf with a fallback to "4".
Change all invocations of "launch_run" to use this derived
number of jobs instead of none or a hard-coded number of "8".
To that end, an additional number of .tcl files have to include
common.tcl now.
Also, use ${PROJECT} in xilinx_mem_32768x32_dp and unify
the related makefiles.
 - copy the sysdef file produced by implementation to root dir
 - in the sw makefile refer to the copies instead of the built
   files within the *.runs directory
Ensure that the build order is
1. ips (in any order)
2. pulpino
3. pulpemu
4. sw (because it depends on files from pulpemu)

Also, use $(MAKE) to facilitate parallel builds.
 - Set default board name to em.avnet.com:zed:0.9
   This corresponds to revision C of the Zedboard since at least
   Vivado 2015.1.
 - Use "board_part" property instead of just "board" as suggested
   by Vivado 2015.1.
This avoids "outdated" synthesis and implementation runs later, e.g.,
when opening the final project later in the GUI.
Not sure what it reports without that, but it is definitely not
correct for the final implementation.
Very similar fixes were applied to the Linux kernel.
This simplifies things a bit and allows us to avoid deleting
the u-boot-xlnx directory like it is already done for the kernel
and buildroot.
This patch also fixes some related dependency problems.

squash! fpga/sw: move git checkouts into the config targets

das mit dem "the ..."
Avoid deleting the u-boot-xlnx repository on make clean to
unify the handling of all sub-repositories.
Also, fix the clean target in case the sub-repositories were
not created yet and clean up spiload.
 - add spiload and gpio_access binaries to .gitignore
 - match all Vivado log files in hsi/
This file can be used to customize the root fs of the SD card

When DEPENDENCIES is passed as first parameter it
prints out all paths that are prerequisites in the
sense of make. Thus the makefile is able to auto-
magically discover them.
This fixes among other things connecting the debug bridge to the
simulator. The problem can be diagnosed by the following message or
similar when executing source tcl_files/run_memdpi.tcl:
Warning: (vsim-3770) Failed to find user specified function 'mem_init' in DPI C/C++ source files.
This patch fixes two problems:

 - The addresses used to access the GPIO interface are wrong.
 - spiload's code is waiting for 0x00000100, i.e. LD0 on,
   everything else including buttons and switches off.
   However, the RISCV code (eoc() in sys_lib/utils.c) does only
   set LD0 and does not care about any other pins.
The error message for the Zybo contained a copy&paste error
that is impossible when using a single point of definition
as with this patch.
 - Combine common code to map the ctrl, gpio and clock regions
 - Map the respective regions only once per execution
 - Let program termination clean up the mappings and file
   descriptors to reduce complexity
This avoids some compiler warnings in cases where the
compiler detects value changes due to the coercion.
Depending on the failing function call spi_load()
would try to close random file pointers and its
return value wouldn't be checked anyway.
Also, the null-checks before free() are useless.
 - support for the old RI5CY is (implicitly) dropped
 - derive -march and -mabi parameters from GCC_MARCH or set of other options
 - make GCC_MARCH easily overridable

NB: This does not update /ci
This also fixes pulp-platform#272 and the like.
The respective files adv_dbg_unit-eps-converted-to.pdf and
pulpino_block-eps-converted-to.pdf were not cleaned up either
but the conversion is unnecessary since we create them
externally in the makefile anyway.
 - Add .PHONY target.
 - Fix prerequisite of of pdf target to include figures.
 - Avoid re-calling make for no reason - call pdflatex twice
   instead.
 - Make all the default target.
Vivado changed behavior in some version between 2015.2 and
2018.3 regarding the automatic removal of unneeded IBUFS/
OBUFs when dealing with netlists. This led to failing
syntheses of pulpemu with errors like:
ERROR: [DRC REQP-127] obuf_loaded: OBUF pulpino_wrap_i/gpio_out_OBUF[16]_inst pin O drives one or more invalid loads. The loads are: ps7_wrapper_i/ps7_i/axi_gpio_emu/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
ERROR: [DRC REQP-127] obuf_loaded: OBUF pulpino_wrap_i/gpio_out_OBUF[17]_inst pin O drives one or more invalid loads. The loads are: ps7_wrapper_i/ps7_i/axi_gpio_emu/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
ERROR: [DRC REQP-127] obuf_loaded: OBUF pulpino_wrap_i/tdo_o_OBUF_inst pin O drives one or more invalid loads. The loads are: ps7_wrapper_i/ps7_i/axi_jtag_emu/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to

This change adds another register around the affected signals, which
apparently calms down Vivado for the synthesis to succeed.
hsi is able to generate device trees from the synthesized
designs. These are superior to some extent to those
automatically generated otherwise (e.g., from the Linux
kernel sources alone). However, they are not always
complete/bootable due to bugs in the Xilinx tools. Notable
exceptions are details on spidev and Ethernet Phys.

Therefore, this patch does *not* replace the existing flow
of having the dts files for each board committed to this
repository. Only if the needed file is not available it
tries to build it with hsi (and warns the user).
Switch defaults to use
 - Xilinx SDK 2018.3 toolchain including linux-xlnx
 - Xilinx FP FMA IP from 7.0 to 7.1
 - buildroot from 2015.05 to 2017.08
 - busybox from 1.23.2 to 1.27.1

Move writing hwdef and sysdef files into implementation phase
and call write_sysdef explicitly (because newer version of
Vivado do not do it automatically anymore).

This was tested on Vivado 2015.1 and 2018.3 with Zedboard only.
m4 in buildroot does not properly build when the host
uses glibc-2.28 but produces errors such as:

freadahead.c: In function 'freadahead':
freadahead.c:92:3: error: #error "Please port gnulib freadahead.c to your platform! Look at the definition of fflush, fread, ungetc on your system, then report this to bug-gnulib."
  #error "Please port gnulib freadahead.c to your platform! Look at the definition of fflush, fread, ungetc on your system, then report this to bug-gnulib."
   ^~~~~

This change adds an upstream patch against buildroot.
At least the Linux kernel in the 2018.3 SDK does hang
on boot when using the serial1 as console for kernel
messages. As a workaround we revert and patch the
respective file to the version of the 2017.4 SDK.
Cf. https://forums.xilinx.com/t5/Embedded-Linux/Kernel-panic-when-using-ttyPS1-as-default-console/m-p/1037792
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant