ci #2013
SamuelRiedelci.yml
on: schedule
tc-gcc
30s
riscv-isa-sim
10s
tc-llvm
48s
verilator
5s
check-control-registers
21s
check-opcodes
3s
Matrix: build-apps-gcc
check-bootrom
9s
Matrix: build-apps-llvm
Matrix: verilator-model
Matrix: run-apps-halide
clean-up
2s
Matrix: clean-up-compile-runs