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[WIP] Fix compilation & optimization of PULP iDMA wrap, register FE
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@da-gazzi
da-gazzi committed Jun 24, 2024
1 parent 187b18e commit e7b61b2
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2 changes: 2 additions & 0 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,8 @@ sources:
- src/backend/idma_obi_write.sv
- src/backend/idma_tilelink_read.sv
- src/backend/idma_tilelink_write.sv
# Level 2
- src/pulp_idma_wrap.sv

# Generated content
- target: rtl
Expand Down
19 changes: 13 additions & 6 deletions src/frontend/reg/tpl/idma_reg.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,17 @@ module idma_${identifier} #(
// register signals
reg_rsp_t [NumRegs-1:0] dma_ctrl_rsp;

always_comb begin
stream_idx_o = '0;
for (int r = 0; r < NumRegs; r++) begin
for (int c = 0; c < NumStreams; c++) begin
if (dma_reg2hw[r].next_id[c].re) begin
stream_idx_o = c;
end
end
end
end

// generate the registers
for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs

Expand Down Expand Up @@ -87,12 +98,8 @@ module idma_${identifier} #(
logic read_happens;
always_comb begin : proc_launch
read_happens = 1'b0;
stream_idx_o = '0;
for (int c = 0; c < NumStreams; c++) begin
read_happens |= dma_reg2hw[i].next_id[c].re;
if (dma_reg2hw[i].next_id[c].re) begin
stream_idx_o = c;
end
end
arb_valid[i] = read_happens;
end
Expand All @@ -114,8 +121,8 @@ module idma_${identifier} #(
% endif

// Protocols
arb_dma_req[i]${sep}src_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.src_protocol);
arb_dma_req[i]${sep}dst_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.dst_protocol);
arb_dma_req[i]${sep}opt.src_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.src_protocol);
arb_dma_req[i]${sep}opt.dst_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.dst_protocol);

// Current backend only supports incremental burst
arb_dma_req[i]${sep}opt.src.burst = axi_pkg::BURST_INCR;
Expand Down
53 changes: 26 additions & 27 deletions src/pulp_idma_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@
`include "idma/typedef.svh"
`include "register_interface/typedef.svh"

`define MY_MAX(a,b) (a > b ? a : b)

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L21 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:21  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:21  column:1}  end:{line:22}}  text:"\n"}
module pulp_idma_wrap #(
parameter int unsigned NB_CORES = 4,
parameter int unsigned AXI_ADDR_WIDTH = 32,
Expand All @@ -38,7 +40,7 @@ module pulp_idma_wrap #(
// mux read ports between tcdm-tcdm and tcdm-axi?

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L40 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:40  column:52}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
parameter bit MUX_READ = 1'b0,
// 4 ports per stream if read ports muxed, otherwise 6
parameter int unsigned NB_TCDM_PORTS_PER_STRM = 4 + (~MUX_READ) * 2
localparam int unsigned NB_TCDM_PORTS_PER_STRM = 4 + (!MUX_READ) * 2

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L43 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:43  column:27}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
) ( // verilog_format: off // verible does not manage to align this :(
input logic clk_i,
input logic rst_ni,
Expand All @@ -47,7 +49,7 @@ module pulp_idma_wrap #(
XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0],

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L49 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:49  column:45}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
hci_core_intf.master tcdm_master[NB_TCDM_PORTS_PER_STRM*NUM_BIDIR_STREAMS-1:0],

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L50 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:50  column:46}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
output axi_req_t [NUM_BIDIR_STREAMS-1:0] ext_master_req_o,
input axi_resp_t [NUM_BIDIR_STREAMS-1:0] ext_master_rsp_i,
input axi_resp_t [NUM_BIDIR_STREAMS-1:0] ext_master_resp_i,
output logic [NB_CORES-1:0] term_event_o,
output logic [NB_CORES-1:0] term_irq_o,
output logic [NB_PE_PORTS-1:0] term_event_pe_o,
Expand Down Expand Up @@ -109,8 +111,12 @@ module pulp_idma_wrap #(
typedef logic [AXI_USER_WIDTH-1:0] user_t;

// // AXI4+ATOP channels typedefs
`AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t)

//`AXI_TYPEDEF_ALL(axi_int, addr_t, id_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t)
// Memory Init typedefs
/// init read request
typedef struct packed {
Expand Down Expand Up @@ -360,18 +366,15 @@ module pulp_idma_wrap #(
localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L366 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:366  column:31}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L367 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:367  column:31}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

function int unsigned max_width(input int unsigned a, b);
return (a > b) ? a : b;
endfunction

typedef struct packed {
init_req_chan_t req_chan;
logic [max_width(init_req_chan_width, obi_a_chan_width)-init_req_chan_width:0] padding;
logic [`MY_MAX(init_req_chan_width, obi_a_chan_width)-init_req_chan_width:0] padding;
} init_read_req_chan_padded_t;

typedef struct packed {
obi_a_chan_t a_chan;
logic [max_width(init_req_chan_width, obi_a_chan_width)-obi_a_chan_width:0] padding;
logic [`MY_MAX(init_req_chan_width, obi_a_chan_width)-obi_a_chan_width:0] padding;
} obi_read_a_chan_padded_t;

typedef union packed {
Expand All @@ -381,12 +384,12 @@ module pulp_idma_wrap #(

typedef struct packed {
axi_aw_chan_t aw_chan;
logic [max_width(axi_aw_chan_width, init_req_chan_width)-axi_aw_chan_width:0] padding;
logic [`MY_MAX(axi_aw_chan_width, init_req_chan_width)-axi_aw_chan_width:0] padding;
} axi_write_aw_chan_padded_t;

typedef struct packed {
init_req_chan_t req_chan;
logic [max_width(axi_aw_chan_width, init_req_chan_width)-init_req_chan_width:0] padding;
logic [`MY_MAX(axi_aw_chan_width, init_req_chan_width)-init_req_chan_width:0] padding;
} init_write_req_chan_padded_t;

typedef union packed {
Expand Down Expand Up @@ -417,7 +420,7 @@ module pulp_idma_wrap #(
.idma_eh_req_t (idma_pkg::idma_eh_req_t),
.idma_busy_t (idma_pkg::idma_busy_t),
.axi_req_t (axi_req_t),
.axi_rsp_t (axi_rsp_t),
.axi_rsp_t (axi_resp_t),
.init_req_t (init_req_t),
.init_rsp_t (init_rsp_t),
.obi_req_t (obi_req_t),
Expand Down Expand Up @@ -475,23 +478,19 @@ module pulp_idma_wrap #(

typedef struct packed {
axi_ar_chan_t ar_chan;
logic [max_width(
axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)
logic [`MY_MAX(
axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
)-axi_ar_chan_width:0] padding;
} axi_read_ar_chan_padded_t;

typedef struct packed {
init_req_chan_t req_chan;
logic [max_width(
axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)
)-init_req_chan_width:0] padding;
logic [`MY_MAX(axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width))-init_req_chan_width:0] padding;

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L488 

Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:488  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
} init_read_req_chan_padded_t;

typedef struct packed {
obi_a_chan_t a_chan;
logic [max_width(
axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)
)-obi_a_chan_width:0] padding;
logic [`MY_MAX(axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width))-obi_a_chan_width:0] padding;

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L493 

Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:493  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
} obi_read_a_chan_padded_t;

typedef union packed {
Expand All @@ -502,12 +501,12 @@ axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)

typedef struct packed {
init_req_chan_t req_chan;
logic [max_width(init_req_chan_width, obi_a_chan_width)-init_req_chan_width:0] padding;
logic [`MY_MAX(init_req_chan_width, obi_a_chan_width)-init_req_chan_width:0] padding;
} init_write_req_chan_padded_t;

typedef struct packed {
obi_a_chan_t a_chan;
logic [max_width(init_req_chan_width, obi_a_chan_width)-obi_a_chan_width:0] padding;
logic [`MY_MAX(init_req_chan_width, obi_a_chan_width)-obi_a_chan_width:0] padding;
} obi_write_a_chan_padded_t;

typedef union packed {
Expand Down Expand Up @@ -538,7 +537,7 @@ axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)
.idma_eh_req_t (idma_pkg::idma_eh_req_t),
.idma_busy_t (idma_pkg::idma_busy_t),
.axi_req_t (axi_req_t),
.axi_rsp_t (axi_rsp_t),
.axi_rsp_t (axi_resp_t),
.init_req_t (init_req_t),
.init_rsp_t (init_rsp_t),
.obi_req_t (obi_req_t),
Expand Down Expand Up @@ -580,17 +579,16 @@ axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)
assign init_write_rsp.rsp_chan.init = '0;
assign init_write_rsp.rsp_valid = init_read_req.req_valid; // might need spill register
assign init_write_rsp.req_ready = 1'b1;
end // block: gen_cpy_in
end // block: gen_streams
end : gen_cpy_in
end : gen_streams


// ------------------------------------------------------
// MUX read OBI connections if specified
// ------------------------------------------------------
for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L589 

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output 
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:589  column:50}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
if (MUX_READ) begin

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L590 

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output 
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:590  column:19}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
obi_pkg::obi_cfg_t sbr_obi_cfg;
assign sbr_obi_cfg = obi_pkg::obi_default_cfg(
localparam obi_pkg::obi_cfg_t sbr_obi_cfg = obi_pkg::obi_default_cfg(

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L591 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:591  column:37}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
AXI_ADDR_WIDTH, AXI_DATA_WIDTH, 0, obi_pkg::ObiMinimalOptionalConfig
);

Expand Down Expand Up @@ -805,3 +803,4 @@ axi_ar_chan_width, max_width(init_req_chan_width, obi_a_chan_width)

end
endmodule
`undef MY_MAX
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