frontend: Add ND-front-ends for both 32 and 64-bit systems (#30, #32, #…

…33) * MARIO: Generate ND frontends automatically * PULP: Modify PULP wrapper to fit the 3D version #33 * PULP: Add a synthesis wrapper for DMAC Wrap #30 * PULP: Closed PR #32 * frontend: Cleanup and homogenization of the register interfaces, remove legacy drivers --------- Co-authored-by: Tobias Senti <[email protected]> Co-authored-by: Simone Di Stasi <[email protected]> Co-authored-by: Alessandro Nadalini <[email protected]>
pulp-platform · Oct 26, 2023 · 2edb5bb · 2edb5bb
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diff --git a/.github/verible.waiver b/.github/verible.waiver
@@ -6,7 +6,7 @@
 # - Thomas Benz <[email protected]>
 
 # Fix this ...
-waive --rule=line-length --location="src/frontends/desc64/idma_desc64.sv"
+waive --rule=line-length --location="src/frontend/desc64/idma_desc64.sv"
 
 # Declare zero-based big-endian unpacked dimensions sized as [N] -> legacy PULP code :S
 waive --rule=unpacked-dimensions-range-ordering --location="src/systems/pulpopen/dmac_wrap.sv"

diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
@@ -28,7 +28,6 @@ jobs:
           SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
         # Exclude generated headers (no license checker support for optional lines)
         exclude_paths: |
-          src/systems/cva6_reg/driver/*.h
           target/sim/vsim/wave/tpl/*.do.tpl
 
   lint-sv:
@@ -47,29 +46,28 @@ jobs:
         fail_on_error: true
         reviewdog_reporter: github-check
 
-  lint-cxx:
-    runs-on: ubuntu-latest
-    steps:
-    -
-      name: Checkout
-      uses: actions/checkout@v3
-    -
-      name: Run Clang-format
-      uses: DoozyX/[email protected]
-      with:
-        extensions: 'c,h,cpp'
-        clangFormatVersion: 14
-        style: >
-          {
-          IndentWidth: 4,
-          ColumnLimit: 100,
-          AlignEscapedNewlines: DontAlign,
-          SortIncludes: false,
-          AllowShortFunctionsOnASingleLine: None,
-          AllowShortIfStatementsOnASingleLine: true,
-          AllowShortLoopsOnASingleLine: true
-          }
-        exclude_paths: src/systems/cva6_reg/driver/*.h target/sim/vsim/wave/tpl/*.tpl
+#  lint-cxx:
+#    runs-on: ubuntu-latest
+#    steps:
+#    -
+#      name: Checkout
+#      uses: actions/checkout@v3
+#    -
+#      name: Run Clang-format
+#      uses: DoozyX/[email protected]
+#      with:
+#        extensions: 'c,h,cpp'
+#        clangFormatVersion: 14
+#        style: >
+#          {
+#          IndentWidth: 4,
+#          ColumnLimit: 100,
+#          AlignEscapedNewlines: DontAlign,
+#          SortIncludes: false,
+#          AllowShortFunctionsOnASingleLine: None,
+#          AllowShortIfStatementsOnASingleLine: true,
+#          AllowShortLoopsOnASingleLine: true
+#          }
 
   lint-python:
     runs-on: ubuntu-latest

diff --git a/Bender.local b/Bender.local
@@ -1,2 +1,2 @@
 overrides:
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
diff --git a/Bender.yml b/Bender.yml
@@ -50,53 +50,39 @@ sources:
   - target: rtl
     files:
       # Level 0
-      - src/midends/idma_nd_midend.sv
+      - src/midend/idma_nd_midend.sv
 
   # Frontends (without inst64)
   - target: rtl
     files:
       # Level 0
-      - src/frontends/desc64/idma_desc64_shared_counter.sv
-      - src/frontends/idma_transfer_id_gen.sv
+      - src/frontend/desc64/idma_desc64_shared_counter.sv
+      - src/frontend/idma_transfer_id_gen.sv
       # Level 1
-      - src/frontends/reg32_2d/idma_reg32_2d.sv
-      - src/frontends/reg64/idma_reg64.sv
-      - src/frontends/reg64_2d/idma_reg64_2d.sv
-      - src/frontends/desc64/idma_desc64_reg_wrapper.sv
+      - src/frontend/desc64/idma_desc64_reg_wrapper.sv
       # Level 2
-      - src/frontends/desc64/idma_desc64.sv
+      - src/frontend/desc64/idma_desc64.sv
 
 
   # Synthesis wrappers
   - target: synth
     files:
       # Level 0
-      - src/frontends/desc64/idma_desc64_synth_pkg.sv
+      - src/frontend/desc64/idma_desc64_synth_pkg.sv
       - src/synth/idma_nd_backend_synth.sv
       # Level 1
-      - src/frontends/desc64/idma_desc64_synth.sv
+      - src/frontend/desc64/idma_desc64_synth.sv
 
   # Testbenches
   - target: test
     files:
       # Level 0
       - test/tb_idma_improved_fifo.sv
       - test/tb_idma_nd_backend.sv
-      - test/frontends/tb_idma_desc64.sv
+      - test/frontend/tb_idma_desc64.sv
       - test/future/idma_tb_per2axi.sv
       - test/future/idma_obi_asserter.sv
       - test/future/TLToAXI4.v
       # Level 1
       - test/future/idma_obi2axi_bridge.sv
       - test/future/idma_tilelink2axi_bridge.sv
-
-# Not yet..
-#  # Systems
-#  - target: all(pulp, not(mchan))
-#    files:
-#      - src/systems/pulpopen/dmac_wrap.sv
-#      - src/systems/pulpopen/synth_dmac_wrap.sv
-#
-#  - target: cva6
-#    files:
-#      - src/systems/cva6_reg/dma_core_wrap.sv
diff --git a/README.md b/README.md
@@ -11,8 +11,9 @@ and in the [PULP Cluster](https://github.com/pulp-platform/pulp).
 iDMA currently implements the following protocols:
 - [AXI4](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)[+ATOPs from AXI5](https://github.com/pulp-platform/axi)
 - [AXI4 Lite](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)
+- [AXI4 Stream](https://developer.arm.com/documentation/ihi0051/b/?lang=en)
 - [OBI v1.5.0](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/obi/OBI-v1.5.0.pdf)
-
+- [TileLink UH v1.8.1](https://starfivetech.com/uploads/tilelink_spec_1.8.1.pdf)
 
 ## Modular Architecture
 iDMA is centered around the idea to split the DMA engine in 3 distinct parts:
@@ -27,7 +28,6 @@ new capabilities.
 
 ## Documentation
 The [latest documentation](https://pulp-platform.github.io/iDMA) can be accessed pre-built.
-The [Morty docs](https://pulp-platform.github.io/iDMA/morty/index.html) provide the generated description of the SystemVerilog files within this repository.
 
 ## Publications
 If you use iDMA in your work or research, you can cite us:
@@ -282,33 +282,31 @@ We currently do not include any free and open-source simulation setup. However,
 a simulation can be launched using:
 
 ```bash
-make gen_rtl_axi.obi.split
-make prepare_sim
-export VSIM="questa-2022.3 vsim"
-$VSIM -c -do "source scripts/compile_vsim.tcl; quit"
+make idma_sim_all
+cd target/sim/vsim
+$VSIM -c -do "source compile.tcl; quit"
 $VSIM -c -t 1ps -voptargs=+acc \
-     +job_file=jobs/multiprotocol/man_mixed.txt \
-     -logfile logs/multiprotocol.simple.vsim.log \
-     -wlf logs/multiprotocol.simple.wlf \
-     tb_idma_backend_r_axi_w_obi \
-     -do "source scripts/start_vsim.tcl; run -all"
+     +job_file=jobs/backend_rw_axi/simple.txt \
+     -logfile rw_axi_simple.log \
+     -wlf rw_axi_simple.wlf \
+     tb_idma_backend_rw_axi \
+     -do "source start.tcl; run -all"
 ```
 with gui:
 ```bash
-make gen_rtl_axi-tilelink.axi.split
-make prepare_sim
-export VSIM="questa-2022.3 vsim"
-$VSIM -c -do "source scripts/compile_vsim.tcl; quit"
+make idma_sim_all
+cd target/sim/vsim
+$VSIM -c -do "source compile.tcl; quit"
 $VSIM -t 1ps -voptargs=+acc \
-     +job_file=jobs/backend/man_tiny.txt \
-     -logfile logs/backend.simple.vsim.log \
-     -wlf logs/backend.medium.wlf \
-     tb_idma_backend_rw_axi_r_tilelink \
-     -do "source scripts/start_vsim.tcl; source scripts/waves/vsim_backend_rw_axi_r_tilelink.do; run -all"
+     +job_file=jobs/backend_rw_axi/simple.txt \
+     -logfile rw_axi_simple.log \
+     -wlf rw_axi_simple.wlf \
+     tb_idma_backend_rw_axi \
+     -do "source start.tcl; source wave/backend_rw_axi.do; run -all"
 ```
 
 Where:
-- `+job_file=jobs/backend/man_simple.txt` can point to any valid [job file](jobs/README.md)
-- `-logfile logs/backend.simple.vsim.log` denotes the log file
-- `-wlf logs/backend.simple.wlf` specifies a wave file
-- `tb_idma_backend` can be any of the supplied testbenches \(`test/tb_idma_*`\)
+- `job_file=jobs/backend_rw_axi/simple.txt` can point to any valid [job file](jobs/README.md)
+- `-logfile rw_axi_simple.log` denotes the log file
+- `-wlf rw_axi_simple.wlf` specifies a wave file
+- `tb_idma_backend_rw_axi` can be any of the supplied testbenches
diff --git a/doc/src/index.rst b/doc/src/index.rst
@@ -43,17 +43,22 @@ The morty docs provide the generated description of the SystemVerilog files with
 
 .. only:: html
 
-  `R_AXI_W_OBI <idma_backend_r_axi_w_obi/index.html>`_
+  `R_AXI_W_OBI Backend <idma_backend_synth_r_axi_w_obi/index.html>`_
 
-  `R_OBI_W_AXI <idma_backend_r_obi_w_axi/index.html>`_
+  `R_OBI_W_AXI Backend <idma_backend_synth_r_obi_w_axi/index.html>`_
 
-  `RW_AXI <idma_backend_rw_axi/index.html>`_
+  `RW_AXI Backend <idma_backend_synth_rw_axi/index.html>`_
 
-.. image:: ../fig/graph/idma_backend_r_axi_w_obi.png
+  `ND Backend <idma_nd_backend_synth/index.html>`_
+
+.. image:: ../fig/graph/idma_backend_synth_r_axi_w_obi.png
+  :width: 600
+
+.. image:: ../fig/graph/idma_backend_synth_r_obi_w_axi.png
   :width: 600
 
-.. image:: ../fig/graph/idma_backend_r_obi_w_axi.png
+.. image:: ../fig/graph/idma_backend_synth_rw_axi.png
   :width: 600
 
-.. image:: ../fig/graph/idma_backend_rw_axi.png
-  :width: 600
+.. image:: ../fig/graph/idma_nd_backend_synth.png
+  :width: 600