Add a CI job for verilator testing

pulp-platform · Jul 3, 2024 · 2044cad · 2044cad
1 parent 27483a6
commit 2044cad
Show file tree

Hide file tree

Showing 4 changed files with 71 additions and 9 deletions.
diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml
@@ -37,3 +37,59 @@ jobs:
           repo: github-mirror/idma
           token: ${{ secrets.GITLAB_TOKEN }}
           poll-count: 10800 # (10800/60=180min=3hours)
+
+  check-verilator:
+    runs-on: ubuntu-22.04
+    steps:
+      -
+        name: Checkout
+        uses: actions/checkout@v3
+      -
+        name: Install Python
+        uses: actions/setup-python@v2
+        with:
+          python-version: 3.9
+          cache: pip
+      -
+        name: Install Python requirements
+        run: pip install -r requirements.txt
+      -
+        name: Install Bender
+        uses: pulp-platform/pulp-actions/bender-install@v2
+        with:
+          version: 0.27.3
+      -
+        name: Install Morty
+        run: |
+          curl --proto '=https' --tlsv1.2 -sLO https://github.com/pulp-platform/morty/releases/download/v0.9.0/morty-ubuntu.22.04-x86_64.tar.gz
+          tar -xvf morty-ubuntu.22.04-x86_64.tar.gz morty
+          rm -f morty-ubuntu.22.04-x86_64.tar.gz
+          chmod 777 morty
+          echo "PATH=.:$PATH" >> ${GITHUB_ENV}
+      - name: Cache Verilator
+        uses: actions/cache@v4
+        with:
+          path: ~/verilator
+          key: ${{ runner.os }}-verilator
+      -
+        name: Install verilator
+        shell: bash
+        run: |
+          sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache libfl2 libfl-dev
+          [ -d ~/verilator ] || git clone -b nba-enable-initial-final https://github.com/RootCubed/verilator.git ~/verilator
+          cd ~/verilator
+          git pull
+          autoconf
+          ./configure
+          make -j `nproc`
+          sudo make install
+      -
+        name: Build sim
+        run: make idma_sim_all
+      -
+        name: Run simulation
+        run: |
+          cd test/backend
+          chmod +x ./idma.sh
+          ./idma.sh
+          ./obj_dir/tb_idma ../../jobs/backend_r_axi_w_obi/simple.yml
diff --git a/idma.mk b/idma.mk
@@ -5,7 +5,7 @@
 # Authors:
 # - Thomas Benz <[email protected]>
 
-BENDER      ?= ./bender
+BENDER      ?= bender
 CAT         ?= cat
 DOT         ?= dot
 GIT         ?= git
@@ -402,7 +402,9 @@ $(IDMA_VLT_DIR)/%_elab.log: $(IDMA_PICKLE_DIR)/sources.json
 	cd $(IDMA_VLT_DIR); $(VERILATOR) $(IDMA_VLT_ARGS) $(IDMA_VLT_PARAMS) -Mdir obj_$* $(IDMA_VLT_TOP).sv --top-module $(IDMA_VLT_TOP) 2> $*_elab.log
 
 $(IDMA_VLT_TEST_DIR)/idma.f: Bender.yml
-	$(BENDER) script verilator -t rtl -t idma_simulation -t snitch_cluster -t verilator -t verilator_test > $@
+	$(BENDER) script verilator -t rtl -t snitch_cluster -t verilator -t verilator_test > $@
+	$(BENDER) script verilator -p common_verification -t simulation >> $@
+	sed -i '/rand_verif_pkg.sv/d' $@
 
 idma_verilator_clean:
 	rm -rf $(IDMA_VLT_DIR)

diff --git a/test/backend/idma.sh b/test/backend/idma.sh
@@ -8,7 +8,8 @@
 # - Liam Braun <[email protected]>
 
 if [ ! -f third_party/rapidyaml.hpp ]; then
-    wget https://github.com/biojppm/rapidyaml/releases/download/v0.7.0/rapidyaml-0.7.0.hpp -O third_party/rapidyaml.hpp
+    mkdir -p ./third_party
+    wget https://github.com/biojppm/rapidyaml/releases/download/v0.7.0/rapidyaml-0.7.0.hpp -O ./third_party/rapidyaml.hpp
 fi
 
 verilator -f idma.f --timing --trace --trace-structs --trace-fst --build --exe -j `nproc` \

diff --git a/test/backend/tb_idma_backend.sv b/test/backend/tb_idma_backend.sv
@@ -257,19 +257,22 @@ module tb_idma_backend #(
             idma_req.pop_front();
 
             $display("Sending request...");
-            req_valid <= #TA '1;
-            #TT;
+            #TA;
+            req_valid = '1;
+            #(TT - TA);
             while (req_ready != '1) begin @(posedge clk); #TT; end
             @(posedge clk);
             $display("Sent request. Waiting for response...");
 
-            req_valid <= #TA '0;
-            rsp_ready <= #TA '1;
-            #TT;
+            #TA;
+            req_valid = '0;
+            rsp_ready = '1;
+            #(TT - TA);
             while (rsp_valid != '1) begin @(posedge clk); #TT; end
             @(posedge clk);
 
-            rsp_ready <= #TA '0;
+            #TA;
+            rsp_ready = '0;
             @(posedge clk);
 
             $display("Request complete.");