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test: Initial Verilator-supported testbench
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RootCubed committed Jul 1, 2024
1 parent 5ebff11 commit 14626f2
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Showing 16 changed files with 1,142 additions and 3 deletions.
2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -11,3 +11,5 @@ working_dir
bender
morty
todo
!target/sim/verilator/driver.cpp
!target/sim/verilator/idma.sh
17 changes: 17 additions & 0 deletions Bender.yml
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Expand Up @@ -124,3 +124,20 @@ sources:
- target: idma_test
files:
- target/rtl/tb_idma_generated.sv

# Verilator
- target: verilator_test
defines:
PORT_AXI4: ~
PORT_OBI: ~
PORT_R_OBI: ~
PORT_W_AXI4: ~
BACKEND_NAME: idma_backend_r_obi_w_axi
files:
- test/drivers/axi_driver_slave.sv
- test/drivers/axi_read.sv
- test/drivers/axi_write.sv
- test/drivers/obi_driver_slave.sv
- test/drivers/obi_read.sv
- test/drivers/obi_write.sv
- test/tb_idma_backend.sv
8 changes: 6 additions & 2 deletions idma.mk
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Expand Up @@ -5,7 +5,7 @@
# Authors:
# - Thomas Benz <[email protected]>

BENDER ?= bender
BENDER ?= ./bender
CAT ?= cat
DOT ?= dot
GIT ?= git
Expand Down Expand Up @@ -399,6 +399,10 @@ $(IDMA_VLT_DIR)/%_elab.log: $(IDMA_PICKLE_DIR)/sources.json
rm -f $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre
cd $(IDMA_VLT_DIR); $(VERILATOR) $(IDMA_VLT_ARGS) $(IDMA_VLT_PARAMS) -Mdir obj_$* $(IDMA_VLT_TOP).sv --top-module $(IDMA_VLT_TOP) 2> $*_elab.log

$(IDMA_VLT_DIR)/idma.f: Bender.yml
mkdir -p $(IDMA_VLT_DIR)
$(BENDER) script verilator -t rtl -t idma_simulation -t snitch_cluster -t verilator -t verilator_test -DSYNTHESIS -DVERILATOR > $@

idma_verilator_clean:
rm -rf $(IDMA_VLT_DIR)

Expand Down Expand Up @@ -482,6 +486,6 @@ idma_pickle_all: $(IDMA_PICKLE_ALL)

idma_hw_all: $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL) $(IDMA_FULL_TB) $(IDMA_HJSON_ALL) $(IDMA_WAVE_ALL)

idma_sim_all: $(IDMA_VCS_DIR)/compile.sh $(IDMA_VSIM_DIR)/compile.tcl
idma_sim_all: $(IDMA_VCS_DIR)/compile.sh $(IDMA_VSIM_DIR)/compile.tcl $(IDMA_VLT_DIR)/idma.f

idma_all: idma_hw_all idma_sim_all idma_doc_all idma_pickle_all
4 changes: 3 additions & 1 deletion target/.gitignore
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@@ -1,3 +1,5 @@
doc
morty
sim/verilator
sim/verilator/*
!sim/verilator/driver.cpp
!sim/verilator/idma.sh
89 changes: 89 additions & 0 deletions target/sim/verilator/driver.cpp
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// Copyright 2024 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51

// Authors:
// - Liam Braun <[email protected]>

#define STR(x) #x
#define EXPAND(x) x
#define STRINGIFY_MACRO(x) STR(x)
#define CONCAT(n1, n2) STRINGIFY_MACRO(EXPAND(n1)EXPAND(n2))

#define HDR_NAME_STR CONCAT(VNAME,.h)
#define DPI_HDR_STR CONCAT(VNAME,__Dpi.h)
#define SYMS_HDR_STR CONCAT(VNAME,__Syms.h)

#include <verilated.h>
#include HDR_NAME_STR
#include DPI_HDR_STR
#include SYMS_HDR_STR

#include <stdio.h>
#include <stdlib.h>
#include <deque>
#include <map>
#include <iostream>

std::map<uint32_t, uint32_t> memory_accesses;
uint32_t curr_access_id = 0xA5A50000;
size_t invalid_writes = 0;

uint32_t copy_from = 0x1000;
uint32_t copy_to = 0x5000;
uint32_t copy_size = 256;

std::string vNameStr = STRINGIFY_MACRO(VNAME);

void idma_read(int addr, int *data, int *delay) {
printf("[DRIVER] Read from %08x: %08x\n", addr, curr_access_id);
*data = curr_access_id;
*delay = 5000;
memory_accesses.insert({addr, curr_access_id});
curr_access_id++;
}

void idma_write(int w_addr, int w_data) {
uint32_t orig_addr = w_addr + copy_from - copy_to;
printf("[DRIVER] Write %08x to %08x (original address: %08x)\n", w_data, w_addr, orig_addr);
if (memory_accesses.count(orig_addr) == 0) {
printf("[DRIVER] Write is invalid (never read from there)\n");
invalid_writes++;
} else if (memory_accesses.at(orig_addr) != w_data) {
printf("[DRIVER] Write is invalid (wrong value)\n");
invalid_writes++;
}
}

typedef struct {
unsigned int dst_addr;
unsigned int src_addr;
unsigned int length;
} idma_req_t;

int main(int argc, char **argv) {
// Verilated::debug(1);

Verilated::commandArgs(argc, argv);
VNAME *idma = new VNAME();
Verilated::traceEverOn(true);
svSetScope(svGetScopeFromName(("TOP." + vNameStr.substr(1)).c_str()));
int cycs = 0;
while (!Verilated::gotFinish() && cycs++ < 100000) {
if (cycs == 100) {
printf("Pushing request\n");
idma->add_request(copy_size, copy_from, copy_to);
}

idma->eval();
if (!idma->eventsPending()) break;
Verilated::time(idma->nextTimeSlot());
}

idma->final();
delete idma;

printf("Testbench terminated. Invalid writes: %ld\n", invalid_writes);

return 0;
}
17 changes: 17 additions & 0 deletions target/sim/verilator/idma.sh
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#!/bin/bash

# Copyright 2024 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

# Authors:
# - Liam Braun <[email protected]>

verilator -f idma.f --timing --trace --trace-structs --exe --build --structs-packed -j `nproc` \
-Wno-REDEFMACRO -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-MODDUP -Wno-PINMISSING \
-Wno-WIDTH -Wno-TIMESCALEMOD \
-Wno-SPLITVAR \
-CFLAGS "-DVNAME=Vtb_idma_backend" \
--top tb_idma_backend \
--cc driver.cpp \
-o tb_idma
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