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Initial ecc llc integration #125

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wants to merge 37 commits into from
Closed

Initial ecc llc integration #125

wants to merge 37 commits into from

Commits on Mar 14, 2024

  1. hw: Update axi_vga to fix performance issue (#113) 

    * Bender.yml: Update dependencies

* axi_vga: Bump version to include an essential performance update

* Bender.yml: Switch to released version

* doc: Add new parameters, fix typo

---------

Co-authored-by: Paul Scheffler <[email protected]>
    @thommythomaso @paulsc96
    thommythomaso and paulsc96 authored Mar 14, 2024
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Commits on Mar 15, 2024

  1. hw: Disable CVA6 FP8ALT support (#114)

    @lucabertaccini
    lucabertaccini authored Mar 15, 2024
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Commits on Apr 18, 2024

  1. make: Ensure correct path to xilinx.mk (#116) 

    Co-authored-by: Philippe Sauter <[email protected]>
    @phsauter
    phsauter and Philippe Sauter authored Apr 18, 2024
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Commits on Apr 25, 2024

  1. target/xilinx: Fix typo in type parameter (#123) 

    Fix a typo in the `reg_rsp_t` parameter. This is not very critical as
it isn't used, but perhaps it can prevent future headache.

Signed-off-by: Nils Wistoff <[email protected]>
    @niwis
    niwis authored Apr 25, 2024
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Commits on May 10, 2024

  1. Integrate HMR unit for CVA6 redundancy.

    Yvan Tortorella committed May 10, 2024
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  2. Add clic virtualization and LLC partitioning.

    Yvan Tortorella committed May 10, 2024
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  3. Add clic virtualization and LLC partitioning.

    Yvan Tortorella committed May 10, 2024
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  4. target/sim: Add JTAG tasks for reg access and preloading (#103) 

    * target/sim: Add JTAG tasks to read/write 32b registers

* target/sim: Add JTAG task to halt and load binary

Can be used by platforms to halt CVA6 and preload a shared memory when
execution happens on domains different than Cheshire.

* target/sim: Clean up added tasks

---------

Co-authored-by: Paul Scheffler <[email protected]>
    @alex96295 @paulsc96
    2 people authored and Yvan Tortorella committed May 10, 2024
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  5. Bump CVA6-SDK tu fetch buildroot through HTTPS.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  6. Bump nonfree to filter out SPI fake errors.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  7. Add selectable AXI cut between core and ID remap.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  8. Propagate FullBandwidth parameter to atomics.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  9. Update atomics tu not include ID queue optimization.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  10. Integrate iDMA v0.6.

    Yvan Tortorella committed May 10, 2024
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  11. Bump axi RISC-V atomics.

    Yvan Tortorella committed May 10, 2024
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  12. Bump iDMA to v0.6.2

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  13. Bump dependencies.

    Yvan Tortorella authored and Yvan Tortorella committed May 10, 2024
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  14. Fix Bender.lock.

    Yvan Tortorella committed May 10, 2024
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Commits on May 14, 2024

  1. Add AXI cut to solve timing loop in DMA wrap.

    Yvan Tortorella committed May 14, 2024
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Commits on May 16, 2024

  1. Bump common cells to fix FFARNC macro.

    Yvan Tortorella committed May 16, 2024
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  2. Bump CVA6.

    Yvan Tortorella committed May 16, 2024
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Commits on May 22, 2024

  1. Use AXI-dedicated checker for CVA6 and bump redundancy cells accordin… 

    …gly.
    Yvan Tortorella committed May 22, 2024
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Commits on May 27, 2024

  1. Properly connect output AXI bus if no redundancy is enabled.

    Yvan Tortorella committed May 27, 2024
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  2. Bump CVA6 for ECC in TLB.

    Yvan Tortorella committed May 27, 2024
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  3. Bump CVA6 to extend ECC also in TLB tags.

    Yvan Tortorella committed May 27, 2024
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  4. Bump CVA6.

    Yvan Tortorella committed May 27, 2024
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Commits on May 28, 2024

  1. Integrate HMR unit for CVA6 redundancy.

    @Aquaticfuller
    Yvan Tortorella authored and Aquaticfuller committed May 28, 2024
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  2. Initial ecc llc cheshire integration

    @Aquaticfuller
    Aquaticfuller committed May 28, 2024
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  3. update the axi_llc and redundancy_cells dependency

    @Aquaticfuller
    Aquaticfuller committed May 28, 2024
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  4. Update axi_llc and redundancy_cells deps, axi_llc now reports ecc scr… 

    …ubber uncorrectable error to cheshire
    @Aquaticfuller
    Aquaticfuller committed May 28, 2024
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  5. Update the axi_llc and redundancy_cells, the redundancy_cells has reb… 

    …ased to the master branch
    @Aquaticfuller
    Aquaticfuller committed May 28, 2024
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Commits on May 29, 2024

  1. Update axi_llc dep

    @Aquaticfuller
    Aquaticfuller committed May 29, 2024
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Commits on May 31, 2024

  1. Update axi_llc dep, fix a parameter issue for synthesis

    @Aquaticfuller
    Aquaticfuller committed May 31, 2024
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Commits on Jun 10, 2024

  1. [BENDER] Update the axi_llc and redundancy_cells dependencies, the ti… 

    …ming cut version.
    @Aquaticfuller
    Aquaticfuller committed Jun 10, 2024
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Commits on Jul 10, 2024

  1. [BENDER] Update axi_llc dep.

    @Aquaticfuller
    Aquaticfuller committed Jul 10, 2024
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Commits on Jul 16, 2024

  1. Bump axi_llc dep for uncorrectable error handling

    @Aquaticfuller
    Aquaticfuller committed Jul 16, 2024
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  2. [Bender] Bump axi_llc and common_cells dep.

    @Aquaticfuller
    Aquaticfuller committed Jul 16, 2024
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