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treewide: Connect LLC performance counters to cheshire regs #119

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treewide: Connect LLC performance counters to cheshire regs #119

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dde2955
treewide: Connect LLC performance counters to cheshire regs
alex96295 Apr 18, 2024
2560494
hw: Connect number of LLC accesses info to cheshire regs
alex96295 Apr 19, 2024
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18 changes: 18 additions & 0 deletions hw/cheshire_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -537,6 +537,24 @@ package cheshire_pkg;
};
endfunction

///////////
// LLC //
///////////

// LLC performance counter events.
typedef enum word_bt {
HitWriteCache = 0,
HitReadCache = 1,
MissWriteCache = 2,
MissReadCache = 3,
RefillWrite = 4,
RefillRead = 5,
EvictWrite = 6,
EvictRead = 7,
WAccess = 8,
RAccess = 9
} llc_evts_e;

////////////////
// Defaults //
////////////////
Expand Down
83 changes: 79 additions & 4 deletions hw/cheshire_soc.sv
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Expand Up @@ -433,6 +433,23 @@
axi_slv_req_t axi_llc_cut_req;
axi_slv_rsp_t axi_llc_cut_rsp;

// All LLC events
axi_llc_pkg::events_t axi_llc_evts_all;

// Selected LLC events
localparam int unsigned LlcNumEvts = 10;
localparam int unsigned LlcEvtCntWidth = 32;

logic [LlcNumEvts-1:0] llc_evts;
logic [LlcNumEvts-1:0][LlcEvtCntWidth-1:0] llc_evt_cnts;

typedef struct packed {
logic [LlcEvtCntWidth-1:0] write;
logic [LlcEvtCntWidth-1:0] read;
} llc_cnt_t;

llc_cnt_t llc_hit_cnt_cache, llc_miss_cnt_cache, llc_refill_cnt, llc_evict_cnt, llc_access_cnt_cache;

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[verible-verilog-lint] hw/cheshire_soc.sv#L451 

Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:451  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

if (Cfg.LlcOutConnect) begin : gen_llc_atomics

axi_slv_req_t axi_llc_amo_req;
Expand Down Expand Up @@ -527,17 +544,65 @@
.cached_start_addr_i ( addr_t'(Cfg.LlcOutRegionStart) ),
.cached_end_addr_i ( addr_t'(Cfg.LlcOutRegionEnd) ),
.spm_start_addr_i ( addr_t'(AmSpm) ),
.axi_llc_events_o ( /* TODO: connect me to regs? */ )
.axi_llc_events_o ( axi_llc_evts_all )
);

// LLC events array comprises 24 17-bit `event_num_bytes_t` data structures
// and 4 1-bit event signals. The 24 structs track, for various events, (i) a
// level-sensitive signal corresponding to a handshake (1-bit `active` field),
// and (ii) the number of transferred bytes (16-bits `num_bytes` field) during
// the handshake. The 4 remaining 1-bit signals perform high-level tracking of
// evict, refill, write and read requests. We filter all this information and
// extract the `active` events for accesses to the LLC (w/r), hits (w/r),
// misses (w/r), refills (w/r) and evictions (w/r) to count how frequently an
// event happened, and collect this number in a register.

assign llc_evts = { axi_llc_evts_all.ar_desc_cache.active, axi_llc_evts_all.aw_desc_cache.active,

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[verible-verilog-lint] hw/cheshire_soc.sv#L560 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:560  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
axi_llc_evts_all.evict_read.active, axi_llc_evts_all.evict_write.active,
axi_llc_evts_all.refill_read.active, axi_llc_evts_all.refill_write.active,
axi_llc_evts_all.miss_read_cache.active, axi_llc_evts_all.miss_write_cache.active,

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[verible-verilog-lint] hw/cheshire_soc.sv#L563 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:563  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
axi_llc_evts_all.hit_read_cache.active, axi_llc_evts_all.hit_write_cache.active

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[verible-verilog-lint] hw/cheshire_soc.sv#L564 

Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:564  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
};

assign llc_hit_cnt_cache.write = llc_evt_cnts[HitWriteCache];
assign llc_hit_cnt_cache.read = llc_evt_cnts[HitReadCache];
assign llc_miss_cnt_cache.write = llc_evt_cnts[MissWriteCache];
assign llc_miss_cnt_cache.read = llc_evt_cnts[MissReadCache];
assign llc_refill_cnt.write = llc_evt_cnts[RefillWrite];
assign llc_refill_cnt.read = llc_evt_cnts[RefillRead];
assign llc_evict_cnt.write = llc_evt_cnts[EvictWrite];
assign llc_evict_cnt.read = llc_evt_cnts[EvictRead];
assign llc_access_cnt_cache.write = llc_evt_cnts[WAccess];
assign llc_access_cnt_cache.read = llc_evt_cnts[RAccess];

for (genvar i=0; i < LlcNumEvts; i++) begin : gen_llc_evt_cntrs
counter #(
.WIDTH ( LlcEvtCntWidth )
) i_llc_evt_cnt (
.clk_i,
.rst_ni,
.clear_i ( 1'b0 ),
.en_i ( llc_evts[i] ),
.load_i ( '0 ),
.down_i ( 1'b0 ),
.d_i ( '0 ),
.q_o ( llc_evt_cnts[i] ),
.overflow_o( /* NOT CONNECTED */ )
);
end

end else if (Cfg.LlcOutConnect) begin : gen_llc_bypass

assign axi_llc_mst_req_o = axi_llc_cut_req;
assign axi_llc_cut_rsp = axi_llc_mst_rsp_i;
assign axi_llc_mst_req_o = axi_llc_cut_req;
assign axi_llc_cut_rsp = axi_llc_mst_rsp_i;
assign axi_llc_evts_all = '0;
assign llc_evt_cnts = '0;

end else begin : gen_llc_stubout

assign axi_llc_mst_req_o = '0;
assign axi_llc_mst_req_o = '0;
assign axi_llc_evts_all = '0;
assign llc_evt_cnts = '0;

end

Expand Down Expand Up @@ -998,6 +1063,16 @@
bus_err : Cfg.BusErr
},
llc_size : get_llc_size(Cfg),
llc_hit_cnt_write_cache : llc_hit_cnt_cache.write,
llc_hit_cnt_read_cache : llc_hit_cnt_cache.read,
llc_miss_cnt_write_cache : llc_miss_cnt_cache.write,
llc_miss_cnt_read_cache : llc_miss_cnt_cache.read,
llc_refill_cnt_write : llc_refill_cnt.write,
llc_refill_cnt_read : llc_refill_cnt.read,
llc_evict_cnt_write : llc_evict_cnt.write,
llc_evict_cnt_read : llc_evict_cnt.read,
llc_access_cnt_write_cache : llc_access_cnt_cache.write,
llc_access_cnt_read_cache : llc_access_cnt_cache.read,
vga_params : '{
red_width : Cfg.VgaRedWidth,
green_width : Cfg.VgaGreenWidth,
Expand Down
154 changes: 122 additions & 32 deletions hw/regs/cheshire_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
package cheshire_reg_pkg;

// Address widths within the block
parameter int BlockAw = 7;
parameter int BlockAw = 8;

////////////////////////////
// Typedefs for registers //
Expand Down Expand Up @@ -75,6 +75,46 @@ package cheshire_reg_pkg;
logic [31:0] d;
} cheshire_hw2reg_llc_size_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_hit_cnt_write_cache_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_hit_cnt_read_cache_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_miss_cnt_write_cache_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_miss_cnt_read_cache_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_refill_cnt_write_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_refill_cnt_read_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_evict_cnt_write_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_evict_cnt_read_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_access_cnt_write_cache_reg_t;

typedef struct packed {
logic [31:0] d;
} cheshire_hw2reg_llc_access_cnt_read_cache_reg_t;

typedef struct packed {
struct packed {
logic [7:0] d;
Expand All @@ -89,39 +129,59 @@ package cheshire_reg_pkg;

// HW -> register type
typedef struct packed {
cheshire_hw2reg_boot_mode_reg_t boot_mode; // [166:165]
cheshire_hw2reg_rtc_freq_reg_t rtc_freq; // [164:133]
cheshire_hw2reg_platform_rom_reg_t platform_rom; // [132:101]
cheshire_hw2reg_num_int_harts_reg_t num_int_harts; // [100:69]
cheshire_hw2reg_hw_features_reg_t hw_features; // [68:56]
cheshire_hw2reg_llc_size_reg_t llc_size; // [55:24]
cheshire_hw2reg_boot_mode_reg_t boot_mode; // [486:485]
cheshire_hw2reg_rtc_freq_reg_t rtc_freq; // [484:453]
cheshire_hw2reg_platform_rom_reg_t platform_rom; // [452:421]
cheshire_hw2reg_num_int_harts_reg_t num_int_harts; // [420:389]
cheshire_hw2reg_hw_features_reg_t hw_features; // [388:376]
cheshire_hw2reg_llc_size_reg_t llc_size; // [375:344]
cheshire_hw2reg_llc_hit_cnt_write_cache_reg_t llc_hit_cnt_write_cache; // [343:312]
cheshire_hw2reg_llc_hit_cnt_read_cache_reg_t llc_hit_cnt_read_cache; // [311:280]
cheshire_hw2reg_llc_miss_cnt_write_cache_reg_t llc_miss_cnt_write_cache; // [279:248]
cheshire_hw2reg_llc_miss_cnt_read_cache_reg_t llc_miss_cnt_read_cache; // [247:216]
cheshire_hw2reg_llc_refill_cnt_write_reg_t llc_refill_cnt_write; // [215:184]
cheshire_hw2reg_llc_refill_cnt_read_reg_t llc_refill_cnt_read; // [183:152]
cheshire_hw2reg_llc_evict_cnt_write_reg_t llc_evict_cnt_write; // [151:120]
cheshire_hw2reg_llc_evict_cnt_read_reg_t llc_evict_cnt_read; // [119:88]
cheshire_hw2reg_llc_access_cnt_write_cache_reg_t llc_access_cnt_write_cache; // [87:56]
cheshire_hw2reg_llc_access_cnt_read_cache_reg_t llc_access_cnt_read_cache; // [55:24]
cheshire_hw2reg_vga_params_reg_t vga_params; // [23:0]
} cheshire_hw2reg_t;

// Register offsets
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_0_OFFSET = 7'h 0;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_1_OFFSET = 7'h 4;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_2_OFFSET = 7'h 8;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_3_OFFSET = 7'h c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_4_OFFSET = 7'h 10;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_5_OFFSET = 7'h 14;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_6_OFFSET = 7'h 18;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_7_OFFSET = 7'h 1c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_8_OFFSET = 7'h 20;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_9_OFFSET = 7'h 24;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_10_OFFSET = 7'h 28;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_11_OFFSET = 7'h 2c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_12_OFFSET = 7'h 30;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_13_OFFSET = 7'h 34;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_14_OFFSET = 7'h 38;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_15_OFFSET = 7'h 3c;
parameter logic [BlockAw-1:0] CHESHIRE_BOOT_MODE_OFFSET = 7'h 40;
parameter logic [BlockAw-1:0] CHESHIRE_RTC_FREQ_OFFSET = 7'h 44;
parameter logic [BlockAw-1:0] CHESHIRE_PLATFORM_ROM_OFFSET = 7'h 48;
parameter logic [BlockAw-1:0] CHESHIRE_NUM_INT_HARTS_OFFSET = 7'h 4c;
parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 7'h 50;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 7'h 54;
parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 7'h 58;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_0_OFFSET = 8'h 0;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_1_OFFSET = 8'h 4;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_2_OFFSET = 8'h 8;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_3_OFFSET = 8'h c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_4_OFFSET = 8'h 10;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_5_OFFSET = 8'h 14;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_6_OFFSET = 8'h 18;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_7_OFFSET = 8'h 1c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_8_OFFSET = 8'h 20;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_9_OFFSET = 8'h 24;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_10_OFFSET = 8'h 28;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_11_OFFSET = 8'h 2c;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_12_OFFSET = 8'h 30;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_13_OFFSET = 8'h 34;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_14_OFFSET = 8'h 38;
parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_15_OFFSET = 8'h 3c;
parameter logic [BlockAw-1:0] CHESHIRE_BOOT_MODE_OFFSET = 8'h 40;
parameter logic [BlockAw-1:0] CHESHIRE_RTC_FREQ_OFFSET = 8'h 44;
parameter logic [BlockAw-1:0] CHESHIRE_PLATFORM_ROM_OFFSET = 8'h 48;
parameter logic [BlockAw-1:0] CHESHIRE_NUM_INT_HARTS_OFFSET = 8'h 4c;
parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 8'h 50;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 8'h 54;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_WRITE_CACHE_OFFSET = 8'h 58;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_READ_CACHE_OFFSET = 8'h 5c;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_WRITE_CACHE_OFFSET = 8'h 60;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_READ_CACHE_OFFSET = 8'h 64;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_WRITE_OFFSET = 8'h 68;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_READ_OFFSET = 8'h 6c;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_WRITE_OFFSET = 8'h 70;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_READ_OFFSET = 8'h 74;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_OFFSET = 8'h 78;
parameter logic [BlockAw-1:0] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_OFFSET = 8'h 7c;
parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 8'h 80;

// Reset values for hwext registers and their fields
parameter logic [1:0] CHESHIRE_BOOT_MODE_RESVAL = 2'h 0;
Expand All @@ -130,6 +190,16 @@ package cheshire_reg_pkg;
parameter logic [31:0] CHESHIRE_NUM_INT_HARTS_RESVAL = 32'h 0;
parameter logic [12:0] CHESHIRE_HW_FEATURES_RESVAL = 13'h 0;
parameter logic [31:0] CHESHIRE_LLC_SIZE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_HIT_CNT_WRITE_CACHE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_HIT_CNT_READ_CACHE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_MISS_CNT_WRITE_CACHE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_MISS_CNT_READ_CACHE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_REFILL_CNT_WRITE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_REFILL_CNT_READ_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_EVICT_CNT_WRITE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_EVICT_CNT_READ_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_RESVAL = 32'h 0;
parameter logic [31:0] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_RESVAL = 32'h 0;
parameter logic [23:0] CHESHIRE_VGA_PARAMS_RESVAL = 24'h 0;

// Register index
Expand All @@ -156,11 +226,21 @@ package cheshire_reg_pkg;
CHESHIRE_NUM_INT_HARTS,
CHESHIRE_HW_FEATURES,
CHESHIRE_LLC_SIZE,
CHESHIRE_LLC_HIT_CNT_WRITE_CACHE,
CHESHIRE_LLC_HIT_CNT_READ_CACHE,
CHESHIRE_LLC_MISS_CNT_WRITE_CACHE,
CHESHIRE_LLC_MISS_CNT_READ_CACHE,
CHESHIRE_LLC_REFILL_CNT_WRITE,
CHESHIRE_LLC_REFILL_CNT_READ,
CHESHIRE_LLC_EVICT_CNT_WRITE,
CHESHIRE_LLC_EVICT_CNT_READ,
CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE,
CHESHIRE_LLC_ACCESS_CNT_READ_CACHE,
CHESHIRE_VGA_PARAMS
} cheshire_id_e;

// Register width information to check illegal writes
parameter logic [3:0] CHESHIRE_PERMIT [23] = '{
parameter logic [3:0] CHESHIRE_PERMIT [33] = '{
4'b 1111, // index[ 0] CHESHIRE_SCRATCH_0
4'b 1111, // index[ 1] CHESHIRE_SCRATCH_1
4'b 1111, // index[ 2] CHESHIRE_SCRATCH_2
Expand All @@ -183,7 +263,17 @@ package cheshire_reg_pkg;
4'b 1111, // index[19] CHESHIRE_NUM_INT_HARTS
4'b 0011, // index[20] CHESHIRE_HW_FEATURES
4'b 1111, // index[21] CHESHIRE_LLC_SIZE
4'b 0111 // index[22] CHESHIRE_VGA_PARAMS
4'b 1111, // index[22] CHESHIRE_LLC_HIT_CNT_WRITE_CACHE
4'b 1111, // index[23] CHESHIRE_LLC_HIT_CNT_READ_CACHE
4'b 1111, // index[24] CHESHIRE_LLC_MISS_CNT_WRITE_CACHE
4'b 1111, // index[25] CHESHIRE_LLC_MISS_CNT_READ_CACHE
4'b 1111, // index[26] CHESHIRE_LLC_REFILL_CNT_WRITE
4'b 1111, // index[27] CHESHIRE_LLC_REFILL_CNT_READ
4'b 1111, // index[28] CHESHIRE_LLC_EVICT_CNT_WRITE
4'b 1111, // index[29] CHESHIRE_LLC_EVICT_CNT_READ
4'b 1111, // index[30] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE
4'b 1111, // index[31] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE
4'b 0111 // index[32] CHESHIRE_VGA_PARAMS
};

endpackage
Expand Down
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