minor fixes

pulp-platform · Sep 12, 2024 · f729c20 · f729c20
1 parent 1d04d66
commit f729c20
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Showing 6 changed files with 44 additions and 31 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -60,8 +60,8 @@ packages:
     dependencies:
     - common_cells
   axi_vga:
-    revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
-    version: 0.1.3
+    revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e
+    version: 0.1.4
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:
@@ -162,7 +162,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp-ethernet:
-    revision: 674fe92a3fcdbde3afe818570a685d7f0923f020
+    revision: a8e69091528d5e8d2a7091082643e5a7c81d2ffd
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git
@@ -174,8 +174,8 @@ packages:
     - idma
     - register_interface
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "674fe92"  } # branch: chs-hs
+  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "a8e6909"  } # branch: chs-hs
 
 export_include_dirs:
   - hw/include

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -1310,8 +1310,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       .BufferDepth         ( 32'd2             ),
       .TFLenWidth          ( 32'd20            ),
       .MemSysDepth         ( 32'd0             ),
-      .TxFifoLogDepth      ( 32'd10            ),
-      .RxFifoLogDepth      ( 32'd10            ),
+      .TxFifoLogDepth      ( 32'd5             ),
+      .RxFifoLogDepth      ( 32'd5             ),
       .axi_req_t           ( axi_mst_req_t     ),
       .axi_rsp_t           ( axi_mst_rsp_t     ),
       .reg_req_t           ( reg_req_t         ),

diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c
@@ -19,6 +19,7 @@
 #define IDMA_RSP_READY_OFFSET        0x4c
 #define IDMA_RSP_VALID_OFFSET        0x50
 #define IDMA_RX_EN_OFFSET            0x54
+#define ETH_MDIO_OFFSET              0x8
 
 #define PLIC_BASE                    0x04000000
 #define RV_PLIC_PRIO19_REG_OFFSET    0x4c
@@ -37,7 +38,7 @@
 #define TX_BASE 0x14000000
 #define RX_BASE 0x14001000
 
-#define PRINTF_ON
+//#define PRINTF_ON
 
 int main(void) { 
 
@@ -67,7 +68,7 @@ int main(void) {
 
   *reg32(ETH_BASE, MACLO_OFFSET)          = 0x00890702;
   // High 16 bit Mac Address
-  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00002301;
+  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00802301;
   // DMA Source Address
   *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)  = TX_BASE;
   // DMA Destination Address
@@ -81,12 +82,18 @@ int main(void) {
 
   // Validate Request to DMA
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
+
+  uint32_t *mdio;
+  // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET);  
+  mdio = 0x0300c008;
+  printf("MDIO value: 0x%08X\n", *mdio);
 
-  // rx irq
-  while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) );
   // configure ethernet
   *reg32(ETH_BASE, MACLO_OFFSET)          = 0x00890702;  
-  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00002301;  
+  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00802301; 
+  // rx irq
+  while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) );
+
   // dma length ready, dma can be configured now
   while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET)));
 

diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
@@ -138,7 +138,7 @@ module fixture_cheshire_soc #(
     .eth_txd_o          ( eth_txd     ),
     .eth_txctl_o        ( eth_txctl   ),
     .eth_rstn_o         ( eth_rstn    ),  
-    .eth_mdio_i         ( eth_mdio_i  ),
+    .eth_mdio_i         ( 1'b0        ),// eth_mdio_i
     .eth_mdio_o         ( eth_mdio_o  ),
     .eth_mdio_oe        ( eth_mdio_en ),
     .eth_mdc_o          ( eth_mdc     ),

diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -723,35 +723,38 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   end
 
   initial begin
-
-    @(posedge eth_rx_irq);
+
     @(posedge clk);
-
-    reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address
+     $display("0");
+    reg_drv_rx.send_write( 'h0300c000, 32'h00222222, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);
-
-    reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
+     $display("1");
+    reg_drv_rx.send_write( 'h0300c004, 'h801111, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
+     $display("2");
 
-    while(1) begin
-      reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error);   // req ready 
-      if( dma_en )
-        break;
-      @(posedge clk);
-    end
+    @(posedge clk);
+
+    // while(1) begin
+    //   reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error);   // req ready 
+    //   if( dma_en )
+    //     break;
+    //   @(posedge clk);
+    // end
 
     reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR  
     @(posedge clk);
-
+
+    $display("3");
     reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR
     @(posedge clk);
-
+    $display("4");
     reg_drv_rx.send_write( 'h0300c028, 32'h5,'hf , reg_error); // src protocol
     @(posedge clk);
-
+    $display("5");
     reg_drv_rx.send_write( 'h0300c02c, 32'h0,'hf , reg_error); // dst protocol
     @(posedge clk);
-
+    $display("6");
     reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error);   // req valid
     @(posedge clk);
 
@@ -764,11 +767,14 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
       @(posedge clk);
     end
 
+    @(posedge eth_rx_irq);
+
+
     // Tx test starts here: external back to core
     reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);
 
-    reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
+    reg_drv_rx.send_write( 'h0300c004, 32'h00802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
 
     reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR