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@chaoqun-liang
chaoqun-liang committed May 18, 2024
1 parent 2f0d7d6 commit 1d16b41
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37 changes: 18 additions & 19 deletions hw/cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ module cheshire_soc import cheshire_pkg::*; #(
input logic test_mode_i,
input logic [1:0] boot_mode_i,
input logic rtc_i,
input logic eth_clk_125,
input logic eth_clk_90,
input logic eth_clk125_i,
input logic eth_clk200_i,
// External AXI LLC (DRAM) port
output axi_ext_llc_req_t axi_llc_mst_req_o,
input axi_ext_llc_rsp_t axi_llc_mst_rsp_i,
Expand Down Expand Up @@ -1379,7 +1379,6 @@ module cheshire_soc import cheshire_pkg::*; #(

end


////////////////
// ETHERNET //
////////////////
Expand All @@ -1396,22 +1395,22 @@ module cheshire_soc import cheshire_pkg::*; #(
) i_tx_eth_idma_wrap (
.clk_i,
.rst_ni,

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[verible-verilog-lint] hw/cheshire_soc.sv#L1397 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1397  column:15}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1397  column:15}  end:{line:1398}}  text:"      .rst_ni,\n"}
.eth_clk125_i ( eth_clk_125 ),
.eth_clk125q_i ( eth_clk_90 ),
.phy_rx_clk_i ( eth_rxck_i ),
.phy_rxd_i ( eth_rxd_i ),
.phy_rx_ctl_i ( eth_rxctl_i ),
.phy_tx_clk_o ( eth_txck_o ),
.phy_txd_o ( eth_txd_o ),
.phy_tx_ctl_o ( eth_txctl_o ),
.phy_resetn_o ( eth_rstn_o ),
.phy_intn_i ( 1'b1 ),
.phy_pme_i ( 1'b1 ),
.phy_mdio_i ( eth_mdio_i ),
.phy_mdio_o ( eth_mdio_o ),
.phy_mdio_oe ( eth_mdio_oe ),
.phy_mdc_o ( eth_mdc_o ),
.testmode_i ( 1'b0 ),
.eth_clk_i ( eth_clk125_i ),
.eth_clk200_i ( eth_clk200_i ),
.phy_rx_clk_i ( eth_rxck_i ),
.phy_rxd_i ( eth_rxd_i ),
.phy_rx_ctl_i ( eth_rxctl_i ),
.phy_tx_clk_o ( eth_txck_o ),
.phy_txd_o ( eth_txd_o ),
.phy_tx_ctl_o ( eth_txctl_o ),
.phy_resetn_o ( eth_rstn_o ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1406 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1406  column:45}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1406  column:45}  end:{line:1407}}  text:"      .phy_resetn_o        ( eth_rstn_o   ),\n"}
.phy_intn_i ( 1'b1 ),
.phy_pme_i ( 1'b1 ),
.phy_mdio_i ( eth_mdio_i ),
.phy_mdio_o ( eth_mdio_o ),
.phy_mdio_oe ( eth_mdio_oe ),
.phy_mdc_o ( eth_mdc_o ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1412 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1412  column:45}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1412  column:45}  end:{line:1413}}  text:"      .phy_mdc_o           ( eth_mdc_o    ),\n"}
.testmode_i ( testmode_i ),
.axi_req_o ( axi_in_req[AxiIn.eth] ),
.axi_rsp_i ( axi_in_rsp[AxiIn.eth] ),
.reg_req_i ( reg_out_req[RegOut.ethernet] ),
Expand Down
72 changes: 48 additions & 24 deletions hw/dma_core_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,21 +15,27 @@
`include "register_interface/typedef.svh"

module dma_core_wrap #(
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned AxiIdWidth = 32'd0,
parameter int unsigned AxiUserWidth = 32'd0,
parameter int unsigned AxiSlvIdWidth = 32'd0,
parameter int unsigned TFLenWidth = 32'd0,
parameter int unsigned NumAxInFlight = 32'd0,
parameter int unsigned MemSysDepth = 32'd0,
parameter int unsigned JobFifoDepth = 32'd0,
parameter bit RAWCouplingAvail = 32'd0,
parameter bit IsTwoD = 32'd0,
parameter type axi_mst_req_t = logic,
parameter type axi_mst_rsp_t = logic,
parameter type axi_slv_req_t = logic,
parameter type axi_slv_rsp_t = logic
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned AxiIdWidth = 32'd0,
parameter int unsigned AxiUserWidth = 32'd0,
parameter int unsigned AxiSlvIdWidth = 32'd0,
parameter int unsigned TFLenWidth = 32'd0,
parameter int unsigned NumAxInFlight = 32'd0,
parameter int unsigned MemSysDepth = 32'd0,
parameter int unsigned JobFifoDepth = 32'd0,
parameter bit EnableAxiCut = 1'b1,
parameter bit RAWCouplingAvail = 32'd0,
parameter bit IsTwoD = 32'd0,
parameter type axi_mst_aw_chan_t = logic,
parameter type axi_mst_ar_chan_t = logic,
parameter type axi_mst_w_chan_t = logic,
parameter type axi_mst_r_chan_t = logic,
parameter type axi_mst_b_chan_t = logic,
parameter type axi_mst_req_t = logic,
parameter type axi_mst_rsp_t = logic,
parameter type axi_slv_req_t = logic,
parameter type axi_slv_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -113,8 +119,8 @@ module dma_core_wrap #(
idma_pkg::idma_busy_t busy;
logic me_busy;
// internal AXI channels
axi_mst_req_t axi_read_req, axi_write_req;
axi_mst_rsp_t axi_read_rsp, axi_write_rsp;
axi_mst_req_t axi_read_req, axi_write_req, axi_cut_req;
axi_mst_rsp_t axi_read_rsp, axi_write_rsp, axi_cut_rsp;

axi_to_reg #(
.ADDR_WIDTH( AxiAddrWidth ),
Expand Down Expand Up @@ -323,11 +329,29 @@ module dma_core_wrap #(
) i_axi_rw_join (
.clk_i,
.rst_ni,
.slv_read_req_i ( axi_read_req ),
.slv_read_resp_o ( axi_read_rsp ),
.slv_write_req_i ( axi_write_req ),
.slv_write_resp_o ( axi_write_rsp ),
.mst_req_o ( axi_mst_req_o ),
.mst_resp_i ( axi_mst_rsp_i )
.slv_read_req_i ( axi_read_req ),
.slv_read_resp_o ( axi_read_rsp ),
.slv_write_req_i ( axi_write_req ),
.slv_write_resp_o ( axi_write_rsp ),
.mst_req_o ( axi_cut_req ),
.mst_resp_i ( axi_cut_rsp )
);
endmodule

axi_cut #(
.Bypass ( ~EnableAxiCut ),
.aw_chan_t ( axi_mst_aw_chan_t ),
.w_chan_t ( axi_mst_w_chan_t ),
.b_chan_t ( axi_mst_b_chan_t ),
.ar_chan_t ( axi_mst_ar_chan_t ),
.r_chan_t ( axi_mst_r_chan_t ),
.axi_req_t ( axi_mst_req_t ),
.axi_resp_t ( axi_mst_rsp_t )
) i_axi_cut (
.clk_i,
.rst_ni,
.slv_req_i ( axi_cut_req ),
.slv_resp_o ( axi_cut_rsp ),
.mst_req_o ( axi_mst_req_o ),
.mst_resp_i ( axi_mst_rsp_i )
);
endmodule

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[verible-verilog-lint] hw/dma_core_wrap.sv#L357 

File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output 
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]"  location:{path:"hw/dma_core_wrap.sv"  range:{start:{line:357  column:10}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:357  column:10}  end:{line:358}}  text:"endmodule\n"}
229 changes: 0 additions & 229 deletions hw/idma_core_wrap.sv
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This file was deleted.

4 changes: 1 addition & 3 deletions target/sim/src/fixture_cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,6 @@ module fixture_cheshire_soc #(
logic i2c_scl_en;

logic eth_clk_125;
logic eth_clk_90;
logic eth_rxck;
logic [3:0] eth_rxd;
logic eth_rxctl;
Expand Down Expand Up @@ -129,8 +128,7 @@ module fixture_cheshire_soc #(
.i2c_scl_o ( i2c_scl_o ),
.i2c_scl_i ( i2c_scl_i ),
.i2c_scl_en_o ( i2c_scl_en ),
.eth_clk_125 ( eth_clk_125 ),
.eth_clk_90 ( eth_clk_90 ),
.eth_clk_i ( eth_clk_125 ),
.eth_rxck_i ( eth_rxck ),
.eth_rxd_i ( eth_rxd ),
.eth_rxctl_i ( eth_rxctl ),
Expand Down
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