FuseSoC and XSIM

.gitlab-ci.yml

@@ -39,6 +39,16 @@ synopsys_dc:
         $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert synopsys_dc
       fi
 
+fuse_xsim:
+  stage: build
+  script:
+    - bender sources
+    - /usr/local/anaconda3/bin/python3 -m pip install fusesoc --user
+    - mkdir fusesoc && cd fusesoc
+    - $HOME/.local/bin/fusesoc library add axi ..
+    - $HOME/.local/bin/fusesoc core list
+    - vitis-2022.1-zr $HOME/.local/bin/fusesoc run --tool xsim --target sim --no-export pulp-platform.org::axi:$(cat ../VERSION | sed s/-/./g)
+
 .run_vsim: &run_vsim
   stage: test
   script:

Bender.yml

@@ -9,7 +9,7 @@ package:
 
 dependencies:
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 }
-  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
+  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
 
 export_include_dirs:

CHANGELOG.md

@@ -9,8 +9,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Added
 - Add `axi_dumper` and `axi_dumper_interpret` script to dump log from an AXI bus for debugging purposes.
+- Add FuseSoC and Vivado XSIM limited test to CI
 
 ### Changed
+- Improve compatibility with FuseSoC
+- Improve compatibility with Vivado XSIM
 
 ### Fixed
 

axi.core

@@ -55,9 +55,39 @@ filesets:
       - src/axi_iw_converter.sv
       - src/axi_lite_xbar.sv
       - src/axi_xbar.sv
+      - src/axi_sim_mem.sv
+      - src/axi_test.sv
     file_type : systemVerilogSource
     depend :
       - ">=pulp-platform.org::common_cells:1.26.0"
+  benchs:
+    files:
+      - test/tb_axi_dw_pkg.sv
+      - test/tb_axi_xbar_pkg.sv
+      - test/axi_synth_bench.sv
+      - test/tb_axi_addr_test.sv
+      - test/tb_axi_atop_filter.sv
+      - test/tb_axi_cdc.sv
+      - test/tb_axi_delayer.sv
+      - test/tb_axi_dw_downsizer.sv
+      - test/tb_axi_dw_upsizer.sv
+      - test/tb_axi_fifo.sv
+      - test/tb_axi_isolate.sv
+      - test/tb_axi_iw_converter.sv
+      - test/tb_axi_lite_mailbox.sv
+      - test/tb_axi_lite_regs.sv
+      - test/tb_axi_lite_to_apb.sv
+      - test/tb_axi_lite_to_axi.sv
+      - test/tb_axi_lite_xbar.sv
+      - test/tb_axi_modify_address.sv
+      - test/tb_axi_serializer.sv
+      - test/tb_axi_sim_mem.sv
+      - test/tb_axi_to_axi_lite.sv
+      - test/tb_axi_to_mem_banked.sv
+      - test/tb_axi_xbar.sv
+    file_type : systemVerilogSource
+    depend :
+      - ">=pulp-platform.org::common_verification:0.2.3"
 
 generators:
   axi_intercon_gen:
@@ -113,3 +143,29 @@ generators:
 targets:
   default:
     filesets : [rtl]
+  sim: &sim
+    filesets : [rtl,benchs]
+    description: Simulate the design
+    toplevel: tb_axi_delayer
+  sim_dw_downsizer:
+    <<: *sim
+    toplevel: tb_axi_dw_downsizer
+  sim_addr_test     : { filesets : [rtl,benchs] , toplevel: tb_axi_addr_test      }
+  sim_atop_filter   : { filesets : [rtl,benchs] , toplevel: tb_axi_atop_filter    }
+  sim_cdc           : { filesets : [rtl,benchs] , toplevel: tb_axi_cdc            }
+  sim_delayer       : { filesets : [rtl,benchs] , toplevel: tb_axi_delayer        }
+  sim_dw_pkg        : { filesets : [rtl,benchs] , toplevel: tb_axi_dw_pkg         }
+  sim_dw_upsizer    : { filesets : [rtl,benchs] , toplevel: tb_axi_dw_upsizer     }
+  sim_isolate       : { filesets : [rtl,benchs] , toplevel: tb_axi_isolate        }
+  sim_iw_converter  : { filesets : [rtl,benchs] , toplevel: tb_axi_iw_converter   }
+  sim_lite_mailbox  : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_mailbox   }
+  sim_lite_regs     : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_regs      }
+  sim_lite_to_apb   : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_to_apb    }
+  sim_lite_to_axi   : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_to_axi    }
+  sim_lite_xbar     : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_xbar      }
+  sim_modify_address: { filesets : [rtl,benchs] , toplevel: tb_axi_modify_address }
+  sim_serializer    : { filesets : [rtl,benchs] , toplevel: tb_axi_serializer     }
+  sim_sim_mem       : { filesets : [rtl,benchs] , toplevel: tb_axi_sim_mem        }
+  sim_to_axi_lite   : { filesets : [rtl,benchs] , toplevel: tb_axi_to_axi_lite    }
+  sim_xbar          : { filesets : [rtl,benchs] , toplevel: tb_axi_xbar           }
+  sim_xbar_pkg      : { filesets : [rtl,benchs] , toplevel: tb_axi_xbar_pkg       }

ips_list.yml

@@ -3,7 +3,7 @@ common_cells:
     group: pulp-platform
 
 common_verification:
-    commit: v0.2.0
+    commit: v0.2.3
     group: pulp-platform
 
 tech_cells_generic:

src/axi_test.sv

@@ -1196,7 +1196,13 @@ package axi_test;
           automatic logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask;
           addr = axi_pkg::beat_addr(aw_beat.ax_addr, aw_beat.ax_size, aw_beat.ax_len,
                                     aw_beat.ax_burst, i);
+`ifdef XSIM
+          // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges
+          // Keeping alternate implementation for XSIM only
+          rand_success = std::randomize(w_beat); assert (rand_success);
+`else
           rand_success = w_beat.randomize(); assert (rand_success);
+`endif
           // Determine strobe.
           w_beat.w_strb = '0;
           n_bytes = 2**aw_beat.ax_size;
@@ -1350,8 +1356,13 @@ package axi_test;
         wait (ar_queue.size > 0);
         ar_beat      = ar_queue.peek();
         byte_addr    = axi_pkg::aligned_addr(ar_beat.ax_addr, axi_pkg::size_t'($clog2(DW/8)));
+`ifdef XSIM
+        // std::randomize(r_beat) may behave differently to r_beat.randomize() wrt. limited ranges
+        // Keeping alternate implementation for XSIM only
         rand_success = std::randomize(r_beat); assert(rand_success);
+`else
         rand_success = r_beat.randomize(); assert(rand_success);
+`endif
         if (MAPPED) begin
           // Either use the actual data, or save the random generated.
           for (int unsigned i = 0; i < (DW/8); i++) begin
@@ -1445,7 +1456,13 @@ package axi_test;
         automatic logic rand_success;
         wait (b_wait_cnt > 0 && (aw_queue.size() != 0));
         aw_beat = aw_queue.pop_front();
-        rand_success = b_beat.randomize(); assert(rand_success);
+`ifdef XSIM
+        // std::randomize(b_beat) may behave differently to b_beat.randomize() wrt. limited ranges
+        // Keeping alternate implementation for XSIM only
+        rand_success = std::randomize(b_beat); assert (rand_success);
+`else
+        rand_success = b_beat.randomize(); assert (rand_success);
+`endif
         b_beat.b_id = aw_beat.ax_id;
         if (RAND_RESP && !aw_beat.ax_atop[axi_pkg::ATOP_R_RESP])
           b_beat.b_resp[1] = $random();

test/tb_axi_delayer.sv

@@ -83,7 +83,13 @@ module tb_axi_delayer;
     @(posedge clk);
     repeat (200) begin
         @(posedge clk);
+`ifdef XSIM
+        // std::randomize(ax_beat) may behave differently to ax_beat.randomize() wrt. limited ranges
+        // Keeping alternate implementation for XSIM only
+        rand_success = std::randomize(ax_beat); assert(rand_success);
+`else
         rand_success = ax_beat.randomize(); assert(rand_success);
+`endif
         axi_master_drv.send_aw(ax_beat);
         w_beat.w_data = 'hcafebabe;
         axi_master_drv.send_w(w_beat);

test/tb_axi_dw_pkg.sv

@@ -413,7 +413,7 @@ package tb_axi_dw_pkg       ;
         axi_b_id = slv_port_axi.b_id;
         $display("%0tns > Master: Got last B with ID: %b",
           $time, axi_b_id);
-        if (this.exp_slv_port_b_queue.empty()) begin
+        if (this.exp_slv_port_b_queue.is_empty()) begin
           incr_failed_tests(1)                                                 ;
           $warning("Master: unexpected B beat with ID: %b detected!", axi_b_id);
         end else begin

test/tb_axi_sim_mem.sv

@@ -84,7 +84,13 @@ module tb_axi_sim_mem #(
     drv.reset_master();
     wait (rst_n);
     // AW
-    rand_success = aw_beat.randomize(); assert(rand_success);
+`ifdef XSIM
+    // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges
+    // Keeping alternate implementation for XSIM only
+    rand_success = std::randomize(aw_beat); assert (rand_success);
+`else
+    rand_success = aw_beat.randomize(); assert (rand_success);
+`endif
     aw_beat.ax_addr >>= $clog2(StrbWidth); // align address with data width
     aw_beat.ax_addr <<= $clog2(StrbWidth);
     aw_beat.ax_len = $urandom();
@@ -93,7 +99,13 @@ module tb_axi_sim_mem #(
     drv.send_aw(aw_beat);
     // W beats
     for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin
-      rand_success = w_beat.randomize(); assert(rand_success);
+`ifdef XSIM
+      // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges
+      // Keeping alternate implementation for XSIM only
+      rand_success = std::randomize(w_beat); assert (rand_success);
+`else
+      rand_success = w_beat.randomize(); assert (rand_success);
+`endif
       w_beat.w_strb = '1;
       if (i == aw_beat.ax_len) begin
         w_beat.w_last = 1'b1;

test/tb_axi_xbar_pkg.sv

@@ -283,7 +283,7 @@ package tb_axi_xbar_pkg;
         axi_b_id = masters_axi[i].b_id;
         $display("%0tns > Master %0d: Got last B with id: %b",
                 $time, i, axi_b_id);
-        if (this.exp_b_queue[i].empty()) begin
+        if (this.exp_b_queue[i].is_empty()) begin
           incr_failed_tests(1);
           $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id);
         end else begin
@@ -358,7 +358,7 @@ package tb_axi_xbar_pkg;
       if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin
         incr_conducted_tests(1);
         slv_axi_id = slaves_axi[i].ar_id;
-        if (this.exp_ar_queue[i].empty()) begin
+        if (this.exp_ar_queue[i].is_empty()) begin
           incr_failed_tests(1);
         end else begin
           // check that the ids are the same
@@ -386,7 +386,7 @@ package tb_axi_xbar_pkg;
           $display("%0tns > Master %0d: Got last R with id: %b",
                    $time, i, mst_axi_r_id);
         end
-        if (this.exp_r_queue[i].empty()) begin
+        if (this.exp_r_queue[i].is_empty()) begin
           incr_failed_tests(1);
           $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id);
         end else begin