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Release v0.39.1
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micprog committed Sep 5, 2023
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11 changes: 11 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -7,7 +7,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.

## Unreleased

## 0.39.1 - 2023-09-05

### Added
- `axi_cdc`: Add `SyncStages` parameter.
- `axi_to_mem_interleaved`: Add interface variant.
- `axi_burst_splitter`: Expose `id_queue`'s `FULL_BW` parameter.
- `axi_chan_compare`: Add parameter to allow reordered transactions.
- Add `AXI_HIGHLIGHT` macro to highlight AXI signals.
- Add flat port instantiation macros.

### Fixed
- `axi_test`: Avoid false negatives for misaligned reads in `axi_scoreboard`.
- `axi_to_detailed_mem`: Ensure proper propagation or `err` and `exokay` signals.

## 0.39.0 - 2023-07-20
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2 changes: 1 addition & 1 deletion VERSION
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0.39.0
0.39.1
4 changes: 2 additions & 2 deletions axi.core
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CAPI=2:

name : pulp-platform.org::axi:0.39.0
name : pulp-platform.org::axi:0.39.1

filesets:
rtl:
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- src/axi_xp.sv
file_type : systemVerilogSource
depend :
- ">=pulp-platform.org::common_cells:1.27.0"
- ">=pulp-platform.org::common_cells:1.31.1"
benchs:
files:
- test/tb_axi_dw_pkg.sv
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2 changes: 1 addition & 1 deletion ips_list.yml
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common_cells:
commit: v1.27.0
commit: v1.31.1
group: pulp-platform

common_verification:
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