Enforce more consistent type naming

Unify type naming across modules, using `axi_req_t` for AXI request and `axi_lite_req_t` for axi lite request. May fix some issues for vivado (see HERO). Similar for `resp` types.
pulp-platform · Jan 19, 2022 · 7e00f3e · 7e00f3e
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Added
 
 ### Changed
+- Enforce consistent naming for request and response types. Now uses `axi_req_t` and `axi_resp_t` for axi types, and `axi_lite_req_t` and `axi_lite_resp_t` for axi-lite types.
 
 ### Fixed
 

diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv
@@ -40,22 +40,22 @@ module axi_atop_filter #(
   /// Maximum number of in-flight AXI write transactions
   parameter int unsigned AxiMaxWriteTxns = 0,
   /// AXI request type
-  parameter type req_t  = logic,
+  parameter type axi_req_t  = logic,
   /// AXI response type
-  parameter type resp_t = logic
+  parameter type axi_resp_t = logic
 ) (
   /// Rising-edge clock of both ports
-  input  logic  clk_i,
+  input  logic      clk_i,
   /// Asynchronous reset, active low
-  input  logic  rst_ni,
+  input  logic      rst_ni,
   /// Slave port request
-  input  req_t  slv_req_i,
+  input  axi_req_t  slv_req_i,
   /// Slave port response
-  output resp_t slv_resp_o,
+  output axi_resp_t slv_resp_o,
   /// Master port request
-  output req_t  mst_req_o,
+  output axi_req_t  mst_req_o,
   /// Master port response
-  input  resp_t mst_resp_i
+  input  axi_resp_t mst_resp_i
 );
 
   // Minimum counter width is 2 to detect underflows.
@@ -405,11 +405,11 @@ module axi_atop_filter_intf #(
   `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
   `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
   `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
-  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
-  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
+  `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
+  `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
 
-  req_t  slv_req,  mst_req;
-  resp_t slv_resp, mst_resp;
+  axi_req_t  slv_req,  mst_req;
+  axi_resp_t slv_resp, mst_resp;
 
   `AXI_ASSIGN_TO_REQ(slv_req, slv)
   `AXI_ASSIGN_FROM_RESP(slv, slv_resp)
@@ -422,8 +422,8 @@ module axi_atop_filter_intf #(
   // Maximum number of AXI write bursts outstanding at the same time
     .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),
   // AXI request & response type
-    .req_t           ( req_t              ),
-    .resp_t          ( resp_t             )
+    .axi_req_t       ( axi_req_t          ),
+    .axi_resp_t      ( axi_resp_t         )
   ) i_axi_atop_filter (
     .clk_i,
     .rst_ni,

diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv
@@ -35,19 +35,19 @@ module axi_burst_splitter #(
   parameter int unsigned DataWidth    = 32'd0,
   parameter int unsigned IdWidth      = 32'd0,
   parameter int unsigned UserWidth    = 32'd0,
-  parameter type         req_t        = logic,
-  parameter type         resp_t       = logic
+  parameter type         axi_req_t    = logic,
+  parameter type         axi_resp_t   = logic
 ) (
-  input  logic  clk_i,
-  input  logic  rst_ni,
+  input  logic      clk_i,
+  input  logic      rst_ni,
 
   // Input / Slave Port
-  input  req_t  slv_req_i,
-  output resp_t slv_resp_o,
+  input  axi_req_t  slv_req_i,
+  output axi_resp_t slv_resp_o,
 
   // Output / Master Port
-  output req_t  mst_req_o,
-  input  resp_t mst_resp_i
+  output axi_req_t  mst_req_o,
+  input  axi_resp_t mst_resp_i
 );
 
   typedef logic [AddrWidth-1:0]   addr_t;
@@ -62,28 +62,28 @@ module axi_burst_splitter #(
   `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
 
   // Demultiplex between supported and unsupported transactions.
-  req_t   act_req,  unsupported_req;
-  resp_t  act_resp, unsupported_resp;
+  axi_req_t   act_req,  unsupported_req;
+  axi_resp_t  act_resp, unsupported_resp;
   logic   sel_aw_unsupported, sel_ar_unsupported;
   localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns;
   axi_demux #(
-    .AxiIdWidth   ( IdWidth   ),
-    .aw_chan_t    ( aw_chan_t ),
-    .w_chan_t     ( w_chan_t  ),
-    .b_chan_t     ( b_chan_t  ),
-    .ar_chan_t    ( ar_chan_t ),
-    .r_chan_t     ( r_chan_t  ),
-    .req_t        ( req_t     ),
-    .resp_t       ( resp_t    ),
-    .NoMstPorts   ( 2         ),
-    .MaxTrans     ( MaxTxns   ),
-    .AxiLookBits  ( IdWidth   ),
-    .FallThrough  ( 1'b1      ),
-    .SpillAw      ( 1'b0      ),
-    .SpillW       ( 1'b0      ),
-    .SpillB       ( 1'b0      ),
-    .SpillAr      ( 1'b0      ),
-    .SpillR       ( 1'b0      )
+    .AxiIdWidth   ( IdWidth     ),
+    .aw_chan_t    ( aw_chan_t   ),
+    .w_chan_t     ( w_chan_t    ),
+    .b_chan_t     ( b_chan_t    ),
+    .ar_chan_t    ( ar_chan_t   ),
+    .r_chan_t     ( r_chan_t    ),
+    .axi_req_t    ( axi_req_t   ),
+    .axi_resp_t   ( axi_resp_t  ),
+    .NoMstPorts   ( 2           ),
+    .MaxTrans     ( MaxTxns     ),
+    .AxiLookBits  ( IdWidth     ),
+    .FallThrough  ( 1'b1        ),
+    .SpillAw      ( 1'b0        ),
+    .SpillW       ( 1'b0        ),
+    .SpillB       ( 1'b0        ),
+    .SpillAr      ( 1'b0        ),
+    .SpillR       ( 1'b0        )
   ) i_demux_supported_vs_unsupported (
     .clk_i,
     .rst_ni,
@@ -119,8 +119,8 @@ module axi_burst_splitter #(
   // Respond to unsupported transactions with slave errors.
   axi_err_slv #(
     .AxiIdWidth ( IdWidth               ),
-    .req_t      ( req_t                 ),
-    .resp_t     ( resp_t                ),
+    .axi_req_t  ( axi_req_t             ),
+    .axi_resp_t ( axi_resp_t            ),
     .Resp       ( axi_pkg::RESP_SLVERR  ),
     .ATOPs      ( 1'b0                  ),  // The burst splitter does not support ATOPs.
     .MaxTrans   ( 1                     )   // Splitting bursts implies a low-performance bus.

diff --git a/src/axi_cut.sv b/src/axi_cut.sv
@@ -19,25 +19,25 @@
 /// Breaks all combinatorial paths between its input and output.
 module axi_cut #(
   // bypass enable
-  parameter bit  Bypass    = 1'b0,
+  parameter bit  Bypass     = 1'b0,
   // AXI channel structs
-  parameter type aw_chan_t = logic,
-  parameter type  w_chan_t = logic,
-  parameter type  b_chan_t = logic,
-  parameter type ar_chan_t = logic,
-  parameter type  r_chan_t = logic,
+  parameter type  aw_chan_t = logic,
+  parameter type   w_chan_t = logic,
+  parameter type   b_chan_t = logic,
+  parameter type  ar_chan_t = logic,
+  parameter type   r_chan_t = logic,
   // AXI request & response structs
-  parameter type     req_t = logic,
-  parameter type    resp_t = logic
+  parameter type  axi_req_t = logic,
+  parameter type axi_resp_t = logic
 ) (
-  input logic   clk_i,
-  input logic   rst_ni,
+  input logic       clk_i,
+  input logic       rst_ni,
   // salve port
-  input  req_t  slv_req_i,
-  output resp_t slv_resp_o,
+  input  axi_req_t  slv_req_i,
+  output axi_resp_t slv_resp_o,
   // master port
-  output req_t  mst_req_o,
-  input  resp_t mst_resp_i
+  output axi_req_t  mst_req_o,
+  input  axi_resp_t mst_resp_i
 );
 
   // a spill register for each channel
@@ -145,11 +145,11 @@ module axi_cut_intf #(
   `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
   `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
   `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
-  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
-  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
+  `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
+  `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
 
-  req_t  slv_req,  mst_req;
-  resp_t slv_resp, mst_resp;
+  axi_req_t  slv_req,  mst_req;
+  axi_resp_t slv_resp, mst_resp;
 
   `AXI_ASSIGN_TO_REQ(slv_req, in)
   `AXI_ASSIGN_FROM_RESP(in, slv_resp)
@@ -158,14 +158,14 @@ module axi_cut_intf #(
   `AXI_ASSIGN_TO_RESP(mst_resp, out)
 
   axi_cut #(
-    .Bypass    (    BYPASS ),
-    .aw_chan_t ( aw_chan_t ),
-    .w_chan_t  (  w_chan_t ),
-    .b_chan_t  (  b_chan_t ),
-    .ar_chan_t ( ar_chan_t ),
-    .r_chan_t  (  r_chan_t ),
-    .req_t     (     req_t ),
-    .resp_t    (    resp_t )
+    .Bypass     (     BYPASS ),
+    .aw_chan_t  (  aw_chan_t ),
+    .w_chan_t   (   w_chan_t ),
+    .b_chan_t   (   b_chan_t ),
+    .ar_chan_t  (  ar_chan_t ),
+    .r_chan_t   (   r_chan_t ),
+    .axi_req_t  (  axi_req_t ),
+    .axi_resp_t ( axi_resp_t )
   ) i_axi_cut (
     .clk_i,
     .rst_ni,
@@ -219,11 +219,11 @@ module axi_lite_cut_intf #(
   `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
   `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
   `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
-  `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
-  `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
+  `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
+  `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
 
-  req_t   slv_req,  mst_req;
-  resp_t  slv_resp, mst_resp;
+  axi_req_t   slv_req,  mst_req;
+  axi_resp_t  slv_resp, mst_resp;
 
   `AXI_LITE_ASSIGN_TO_REQ(slv_req, in)
   `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp)
@@ -232,14 +232,14 @@ module axi_lite_cut_intf #(
   `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out)
 
   axi_cut #(
-    .Bypass    (    BYPASS ),
-    .aw_chan_t ( aw_chan_t ),
-    .w_chan_t  (  w_chan_t ),
-    .b_chan_t  (  b_chan_t ),
-    .ar_chan_t ( ar_chan_t ),
-    .r_chan_t  (  r_chan_t ),
-    .req_t     (     req_t ),
-    .resp_t    (    resp_t )
+    .Bypass     (     BYPASS ),
+    .aw_chan_t  (  aw_chan_t ),
+    .w_chan_t   (   w_chan_t ),
+    .b_chan_t   (   b_chan_t ),
+    .ar_chan_t  (  ar_chan_t ),
+    .r_chan_t   (   r_chan_t ),
+    .axi_req_t  (  axi_req_t ),
+    .axi_resp_t ( axi_resp_t )
   ) i_axi_cut (
     .clk_i,
     .rst_ni,

diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv
@@ -16,28 +16,28 @@
 /// Synthesizable module that (randomly) delays AXI channels.
 module axi_delayer #(
   // AXI channel types
-  parameter type aw_chan_t = logic,
-  parameter type  w_chan_t = logic,
-  parameter type  b_chan_t = logic,
-  parameter type ar_chan_t = logic,
-  parameter type  r_chan_t = logic,
+  parameter type  aw_chan_t = logic,
+  parameter type   w_chan_t = logic,
+  parameter type   b_chan_t = logic,
+  parameter type  ar_chan_t = logic,
+  parameter type   r_chan_t = logic,
   // AXI request & response types
-  parameter type     req_t = logic,
-  parameter type    resp_t = logic,
+  parameter type  axi_req_t = logic,
+  parameter type axi_resp_t = logic,
   // delay parameters
   parameter bit          StallRandomInput  = 0,
   parameter bit          StallRandomOutput = 0,
   parameter int unsigned FixedDelayInput   = 1,
   parameter int unsigned FixedDelayOutput  = 1
 ) (
-  input  logic  clk_i,      // Clock
-  input  logic  rst_ni,     // Asynchronous reset active low
+  input  logic      clk_i,      // Clock
+  input  logic      rst_ni,     // Asynchronous reset active low
   // slave port
-  input  req_t  slv_req_i,
-  output resp_t slv_resp_o,
+  input  axi_req_t  slv_req_i,
+  output axi_resp_t slv_resp_o,
   // master port
-  output req_t  mst_req_o,
-  input  resp_t mst_resp_i
+  output axi_req_t  mst_req_o,
+  input  axi_resp_t mst_resp_i
 );
   // AW
   stream_delay #(
@@ -152,11 +152,11 @@ module axi_delayer_intf #(
   `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
   `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
   `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
-  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
-  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
+  `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
+  `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
 
-  req_t  slv_req,  mst_req;
-  resp_t slv_resp, mst_resp;
+  axi_req_t  slv_req,  mst_req;
+  axi_resp_t slv_resp, mst_resp;
 
   `AXI_ASSIGN_TO_REQ(slv_req, slv)
   `AXI_ASSIGN_FROM_RESP(slv, slv_resp)
@@ -170,8 +170,8 @@ module axi_delayer_intf #(
     .b_chan_t          (            b_chan_t ),
     .ar_chan_t         (           ar_chan_t ),
     .r_chan_t          (            r_chan_t ),
-    .req_t             (               req_t ),
-    .resp_t            (              resp_t ),
+    .axi_req_t         (           axi_req_t ),
+    .axi_resp_t        (          axi_resp_t ),
     .StallRandomInput  ( STALL_RANDOM_INPUT  ),
     .StallRandomOutput ( STALL_RANDOM_OUTPUT ),
     .FixedDelayInput   ( FIXED_DELAY_INPUT   ),