Fix issue that PPGTT size/CCS0 setting doesn't work issue in driver_p…

…robe In i915_driver_probe, the guc is not enabled to hack the PPGTT/CCS0 change, move them to i915_pci.c Tracked-On: OAM-124793 Signed-off-by: Wenkui <[email protected]>
projectceladon · Sep 18, 2024 · 79cb629 · 79cb629
1 parent 2517f05
commit 79cb629
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Showing 2 changed files with 8 additions and 20 deletions.
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
@@ -802,21 +802,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return PTR_ERR(i915);
 	}
 
-	/*
-	 * Hack to enable CCS and set ppgtt_size to 47
-	 * on TGL and DG1 for testing purpose
-	 *
-	 */
-	if ((match_info->platform == INTEL_DG1 ||
-	    match_info->platform == INTEL_TIGERLAKE ||
-		match_info->platform == INTEL_ALDERLAKE_S ||
-		match_info->platform == INTEL_ALDERLAKE_P) &&
-	    (i915->params.enable_guc & ENABLE_GUC_SUBMISSION)
-	    && i915->params.enable_guc != -1) {
-		RUNTIME_INFO(i915)->ppgtt_size = 47;
-		RUNTIME_INFO(i915)->platform_engine_mask |= BIT(CCS0);
-	}
-
 	/*
 	 * Force to disable CCS on MTL.
 	 * Will remove this code once CCS enablement is completed on MTL

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
@@ -649,7 +649,8 @@ static const struct intel_device_info tgl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_TIGERLAKE),
 	.__runtime.platform_engine_mask =
-		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(CCS0),
+	.__runtime.ppgtt_size = 47,
 	.has_guc_tlb_invalidation = 1, /* Required for SR-IOV */
 	.has_sriov = 1,
 };
@@ -677,7 +678,7 @@ static const struct intel_device_info dg1_info = {
 	.require_force_probe = 1,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
-		BIT(VCS0) | BIT(VCS2),
+		BIT(VCS0) | BIT(VCS2) | BIT(CCS0),
 	/* Wa_16011227922 */
 	.__runtime.ppgtt_size = 47,
 };
@@ -686,8 +687,10 @@ static const struct intel_device_info adl_s_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ALDERLAKE_S),
 	.__runtime.platform_engine_mask =
-		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(CCS0),
 	.dma_mask_size = 39,
+	.__runtime.ppgtt_size = 47,
+
 	.has_guc_tlb_invalidation = 1, /* Required for SR-IOV */
 	.has_sriov = 1,
 };
@@ -696,8 +699,8 @@ static const struct intel_device_info adl_p_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ALDERLAKE_P),
 	.__runtime.platform_engine_mask =
-		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
-	.__runtime.ppgtt_size = 48,
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(CCS0),
+	.__runtime.ppgtt_size = 47,
 	.dma_mask_size = 39,
 	.has_guc_tlb_invalidation = 1, /* Required for SR-IOV */
 	.has_sriov = 1,