Update soc branch with changes from main

.gitignore

@@ -1,5 +1,7 @@
 **/work*
 **/wally_*.log
+/**/obj_dir*
+/**/gmon*
 
 .nfs*
 
@@ -115,10 +117,10 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
 tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
 sim/branch_BP_GSHARE10.log
 sim/branch_BP_GSHARE16.log
-sim/imperas.log
+sim/questa/imperas.log
 sim/results-error/
 sim/test1.rep
-sim/vsim.log
+sim/questa/vsim.log
 tests/coverage/*.elf
 *.elf.memfile
 sim/*Cache.log
@@ -186,7 +188,10 @@ sim/cfi/*
 sim/branch/*
 sim/obj_dir
 examples/verilog/fulladder/obj_dir
+examples/verilog/fulladder/fulladder.vcd
 config/deriv
+docs/docker/buildroot-config-src
+docs/docker/testvector-generation
 sim/questa/cov
 sim/questa/covhtmlreport/
 sim/questa/logs
@@ -196,3 +201,39 @@ sim/verilator/wkdir
 sim/vcs/logs
 sim/vcs/wkdir
 benchmarks/coremark/coremark_results.csv
+fpga/zsbl/OBJ/*
+fpga/zsbl/bin/*
+sim/*.svg
+sim/vcs/csrc
+sim/vcs/profileReport*
+sim/vcs/program.out
+sim/vcs/sim_out*
+sim/vcs/simprofile_dir
+sim/vcs/ucli.key
+sim/vcs/verdi_config_file
+sim/vcs/vcdplus.vpd
+sim/*/testbench.vcd 
+sim/questa/imperas.log
+sim/questa/functcov.log
+sim/questa/functcov_logs/*
+sim/questa/functcov_ucdbs/*
+sim/questa/functcov
+sim/questa/riscv.ucdb
+sim/questa/riscv.ucdb.log
+sim/questa/riscv.ucdb.summary.log
+sim/questa/riscv.ucdb.testdetails.log
+tests/riscvdv
+examples/verilog/fulladder/csrc/
+examples/verilog/fulladder/profileReport.html
+examples/verilog/fulladder/profileReport.json
+examples/verilog/fulladder/profileReport.txt
+examples/verilog/fulladder/profileReport/
+examples/verilog/fulladder/simprofile_dir/
+examples/verilog/fulladder/simv.daidir/
+examples/verilog/fulladder/ucli.key
+examples/verilog/fulladder/verdi_config_file
+examples/crypto/gfmul/gfmul
+tests/functcov
+tests/functcov/*
+tests/functcov/*/*
+sim/vcs/simprofile*

.gitmodules

@@ -23,6 +23,7 @@
 [submodule "addins/riscv-arch-test"]
 	path = addins/riscv-arch-test
 	url = https://github.com/riscv-non-isa/riscv-arch-test
+	branch = dev
 [submodule "addins/branch-predictor-simulator"]
 	path = addins/branch-predictor-simulator
 	url = https://github.com/ross144/branch-predictor-simulator

Makefile

@@ -2,26 +2,16 @@
 # Top-level Makefile for CORE-V-Wally
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
+SIM = ${WALLY}/sim
+
 all:
-	make install
 	make riscof	
 	make testfloat
 #	make verify
-	make coverage
-	make benchmarks
-
-# install copies over the Makefile.include from riscv-isa-sim
-# And corrects the TARGETDIR path and the RISCV_PREFIX
-
-install:
-	# *** 1/15/23 dh: check if any of this is still needed
-	#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-	#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
-	#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
-	##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
-	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
-	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+#	make coverage
+#	make benchmarks
 
+# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
 riscof:
 	make -C sim
 
@@ -31,21 +21,22 @@ testfloat:
 	cd ${WALLY}/tests/fp; ./create_all_vectors.sh
 
 verify:
-	cd ${WALLY}/sim; ./regression-wally
-	cd ${WALLY}/sim; ./sim-testfloat-batch all
+	cd ${SIM}; ./regression-wally
+	cd ${SIM}/sim; ./sim-testfloat-batch all
 	make imperasdv
 
 imperasdv:
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
 
 imperasdv_cov:
-	touch ${WALLY}/sim/seed0.txt
-	echo "0" > ${WALLY}/sim/seed0.txt
+	touch ${SIM}/seed0.txt
+	echo "0" > ${SIM}/seed0.txt
 #	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
-#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
-	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
-	vcover report -details -html sim/riscv.ucdb
+#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
+#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
+	run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
+	vcover report -details -html ${SIM}/questa/riscv.ucdb
 
 funcovreg:
 	#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
@@ -54,10 +45,69 @@ funcovreg:
 	#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
 	rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
-	vcover report -details -html sim/riscv.ucdb
-
-coverage:
-	cd ${WALLY}/sim; ./regression-wally -coverage -fp
+	vcover report -details -html ${SIM}/questa/riscv.ucdb
+
+
+
+# test_name=riscv_arithmetic_basic_test
+riscvdv: 
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile			>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
+
+riscvdv_functcov:
+	mkdir -p ${SIM}/questa/functcov_logs
+	mkdir -p ${SIM}/questa/functcov_ucdbs
+	cd ${SIM}/questa/functcov_logs && rm -rf *
+	cd ${SIM}/questa/functcov_ucdbs && rm -rf *
+	make riscvdv test_name=riscv_arithmetic_basic_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_amo_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_debug_mode_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_arithmetic_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_mmu_stress_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_full_interrupt_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_hint_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_illegal_instr_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_invalid_csr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_jump_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_loop_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_machine_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_mmu_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_no_fence_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_non_compressed_instr_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_pmp_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_privileged_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_jump_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_sfence_exception_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_unaligned_load_store_test			>> ${SIM}/questa/functcov.log 2>&1
+
+combine_functcov:
+	mkdir -p ${SIM}/questa/functcov
+	mkdir -p ${SIM}/questa/functcov_logs
+	cd ${SIM}/questa/functcov && rm -rf *
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+
+	vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov/*.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	# vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	vcover report -details -html ${SIM}/questa/functcov/functcov.ucdb
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg > ${SIM}/questa/functcov/functcov.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -testdetails -cvg > ${SIM}/questa/functcov/functcov.testdetails.log
+#	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/functcov/functcov.ucdb.summary.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE"  > ${SIM}/questa/functcov/functcov.summary.log
+	grep "Total Coverage By Instance" ${SIM}/questa/functcov/functcov.ucdb.log
+
+remove_functcov_artifacts:
+	rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf
+
+collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
 
 benchmarks:
 	make coremark

README.md

@@ -41,38 +41,46 @@ Clone your fork of the repo and run the setup script. Change <yourgithubid> to y
 	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ source ./setup.sh
 
+If you are installing on a new system without any tools installed please jump to the next section, Toolchain Installation then come back here.
+
 Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
 
 	if [ -f ~/cvw/setup.sh ]; then
 		source ~/cvw/setup.sh
 	fi
 
-Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.
-
-	export [email protected]                # Change this to your Siemens license server
-	export [email protected]                # Change this to your Synopsys license server
-	export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin     # Change this for your path to Questa
-	export SNPSPATH=/cad/synopsys/SYN/bin                               # Change this for your path to Design Compiler
-
 If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
 
 Build the tests and run a regression simulation with Questa to prove everything is installed.  Building tests will take a while.
 
 	$ make
-	$ cd sim
-	$ ./regression-wally       (depends on having Questa installed)
+	$ regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
 
 This section describes the open source toolchain installation.  The
-current version of the toolchain has been tested on Ubuntu and Red
+current version of the toolchain has been tested on Ubuntu and partly on Red
 Hat/Rocky 8 Linux.  Ubuntu works more smoothly and is recommended
-unless you have a compelling need for RedHat.  
+unless you have a compelling need for RedHat.  However, Ubuntu 22.04LTS
+is incompatible with Synopsys Design Compiler.
 
 Ubuntu users can install the tools by running
 
 	$ sudo $WALLY/bin/wally-tool-chain-install.sh
 
+The default installation directory is /opt/riscv defined by the environment variable RISCV. You must copy and edit ~/cvw/site-setup.sh to $RISCV/site-setup.sh.
+
+~/cvw/setup.sh sources $RISCV/site-setup.sh.
+This allows for customization of the site specific information such as commerical licenses and PATH variables.
+
+Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.  If Questa or Design Compiler are already setup on this system then don't set these variables.
+
+	export MGLS_LICENSE_FILE=..         # Change this to your Siemens license server
+	export SNPSLMD_LICENSE_FILE=..      # Change this to your Synopsys license server
+	export QUESTAPATH=..                # Change this for your path to Questa
+	export SNPSPATH=..                  # Change this for your path to Design Compiler
+
+
 See wally-tool-chain-install.sh for a detailed description of each component,
 or to issue the commands one at a time to install on the command line.
 ## Installing EDA Tools
@@ -131,9 +139,54 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to
 ## Adding Cron Job for nightly builds
 
 If you want to add a cronjob you can do the following:
-1) `crontab -e`
-2) add this code:
+1) Set up the email client `mutt` for your distribution
+2) Enter `crontab -e` into a terminal
+3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
 ```
-0 3 * * * BASH_ENV=~/.bashrc bash -l -c "PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh > PATH_TO_LOG_FOLDER/cron.log"
+30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email [email protected],[email protected]"
 ```
 
+# Example wsim commands
+
+wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
+The general syntax is
+wsim <config> <suite or elf file or directory> [--options]
+
+Parameters and options:
+
+	-h, --help                                                   show this help message and exit
+	--sim {questa,verilator,vcs}, -s {questa,verilator,vcs}      Simulator
+	--tb {testbench,testbench_fp}, -t {testbench,testbench_fp}   Testbench
+	--gui, -g                                                    Simulate with GUI
+	--coverage, -c                                               Code & Functional Coverage
+	--fcov, -f                                                   Code & Functional Coverage
+	--args ARGS, -a ARGS                                         Optional arguments passed to simulator via $value$plusargs
+	--vcd, -v                                                    Generate testbench.vcd
+	--lockstep, -l                                               Run ImperasDV lock, step, and compare.
+	--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG                    Retired instruction number to be begin logging.
+	--covlog COVLOG, -d COVLOG                                   Log coverage after n instructions.
+	--elfext ELFEXT, -e ELFEXT                                   When searching for elf files only includes ones which end in this extension
+
+Run basic test with questa
+
+	wsim rv64gc arch64i
+
+Run Questa with gui
+
+	wsim rv64gc wally64priv --gui
+
+Run lockstep against ImperasDV with a single elf file in the --gui.  Lockstep requires single elf.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
+
+Run lockstep against ImperasDV with a single elf file.  Compute coverage.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
+
+Run lockstep against ImperasDV with directory file.  
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
+
+Run lockstep against ImperasDV with directory file and specify specific extension.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf

benchmarks/coremark/Makefile

@@ -5,14 +5,14 @@
 PORT_DIR = $(CURDIR)/riscv64-baremetal
 cmbase= $(WALLY)/addins/coremark
 work_dir= $(WALLY)/benchmarks/coremark/work
-XLEN ?=64
+XLEN ?=32
 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
 	$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
-#ARCH := rv$(XLEN)gc_zba_zbb_zbc
-ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbc
+ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs
+CONFIG := rv$(XLEN)gc
 #ARCH := rv$(XLEN)gc
 #ARCH := rv$(XLEN)imc_zicsr
 #ARCH := rv$(XLEN)im_zicsr
@@ -27,9 +27,9 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
-run:
-	time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
-	#(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+run: $(work_dir)/coremark.bare.riscv.elf.memfile
+#	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
+	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump