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Trap DV plan: first version #1623
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JeanRochCoulon
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openhwgroup:master
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ThalesSiliconSecurity:trap_dvplan
Nov 13, 2023
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -29,4 +29,5 @@ CV32A6-step1 Design Verification Plan | |
| dvplan_AXI | ||
| dvplan_FENCEI | ||
| dvplan_csr-access | ||
| dvplan_traps | ||
|
|
||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,59 @@ | ||
| !Feature | ||
| next_elt_id: 2 | ||
| name: Illegal Instruction | ||
| id: 0 | ||
| display_order: 0 | ||
| subfeatures: !!omap | ||
| - 000_illegal_instr: !Subfeature | ||
| name: 000_illegal_instr | ||
| tag: VP_traps_F000_S000 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F000_S000_I000 | ||
| description: The behavior upon decoding a reserved instruction is unspecified. | ||
| Opcodes that do not decode to a valid, supported instruction for the CVA6 | ||
| core configuration shall raise an illegal instruction exception. | ||
| reqt_doc: Unprivileged ISA Version 20191213, Chapter 2.2 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when executing any illegal instruction, an exception | ||
| is raised with `mcause` set to 0x2. | ||
| pfc: 3 | ||
| test_type: 3 | ||
| cov_method: 3 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: Covered by ISACOV tests, not yet in ISACOV DV plan | ||
| - 001_mtval: !Subfeature | ||
| name: 001_mtval | ||
| tag: VP_traps_F000_S001 | ||
| next_elt_id: 1 | ||
| display_order: 1 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F000_S001_I000 | ||
| description: When an illegal instruction exception is raised, the corresponding | ||
| instruction is stored into `mtval` CSR. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when any illegal instruction exception is raised, | ||
| `mtval` CSR contains the faulting instruction. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: ZERO_TVAL parameter value? | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,54 @@ | ||
| !Feature | ||
| next_elt_id: 1 | ||
| name: CSR Access | ||
| id: 2 | ||
| display_order: 2 | ||
| subfeatures: !!omap | ||
| - 000_CSR_access: !Subfeature | ||
| name: 000_CSR_access | ||
| tag: VP_traps_F002_S000 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F002_S000_I000 | ||
| description: Attempted access to non-existent CSRs will generate an illegal | ||
| instruction exception. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 2.1 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when accessing any non-existent CSR, an exception | ||
| is raised with `mcause` set to 0x2. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: "Covered by CSR DV plan.\nVP_csr-embedded-access_F001_S002_I000\n | ||
| Verify if `mcause` value check is covered by CSR tests." | ||
| - '001': !VerifItem | ||
| name: '001' | ||
| tag: VP_traps_F002_S000_I001 | ||
| description: Attempted store to read-only CSRs will generate an illegal instruction | ||
| exception. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 2.1 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when storing to any read-only CSR, an exception is | ||
| raised with `mcause` set to 0x2. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: "Covered by CSR DV plan.\nVP_csr-embedded-access_F001_S001_I000\n | ||
| Verify if `mcause` value check is covered by CSR tests." | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| !Feature | ||
| next_elt_id: 1 | ||
| name: Machine Trap Vector | ||
| id: 3 | ||
| display_order: 3 | ||
| subfeatures: !!omap | ||
| - 000_mtvec: !Subfeature | ||
| name: 000_mtvec | ||
| tag: VP_traps_F003_S000 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F003_S000_I000 | ||
| description: '`mtvec` provides the starting value of the Interrupt Vector | ||
| Table as well as the mode (Direct or Vectored) number at the time. Mode | ||
| number is not relevant to exceptions as it only affects the value jumped | ||
| to by interrupts.' | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.7 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that exceptions jump to the base value defined in `mtvec` | ||
| CSR. | ||
| pfc: 3 | ||
| test_type: 3 | ||
| cov_method: 1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: '' | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| !Feature | ||
| next_elt_id: 1 | ||
| name: Machine Exception Program Counter | ||
| id: 5 | ||
| display_order: 5 | ||
| subfeatures: !!omap | ||
| - 000_mepc: !Subfeature | ||
| name: 000_mepc | ||
| tag: VP_traps_F005_S000 | ||
| next_elt_id: 2 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F005_S000_I000 | ||
| description: '`mepc` is set to the `pc` value of the instruction that generates | ||
| an exception.' | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when an exception is raised, `mepc` CSR contains the | ||
| correct `pc`. | ||
| pfc: 3 | ||
| test_type: 3 | ||
| cov_method: 1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: '' | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,106 @@ | ||
| !Feature | ||
| next_elt_id: 1 | ||
| name: Machine Trap Value | ||
| id: 6 | ||
| display_order: 6 | ||
| subfeatures: !!omap | ||
| - 000_mtval_illegal: !Subfeature | ||
| name: 000_mtval_illegal | ||
| tag: VP_traps_F006_S000 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F006_S000_I000 | ||
| description: When an illegal instruction exception is raised, the corresponding | ||
| instruction is stored into `mtval` CSR. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when any illegal instruction exception is raised, | ||
| `mtval` CSR contains the faulting instruction. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: ZERO_TVAL parameter value? | ||
| - 001_mtval_misaligned: !Subfeature | ||
| name: 001_mtval_misaligned | ||
| tag: VP_traps_F006_S001 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F006_S001_I000 | ||
| description: When an address misaligned exception is raised, the corresponding | ||
| address is stored into `mtval` CSR. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when any address misaligned exception is raised, `mtval` | ||
| CSR contains the address of the portion of the access causing the fault. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: ZERO_TVAL parameter value? | ||
| - 002_mtval_access: !Subfeature | ||
| name: 002_mtval_access | ||
| tag: VP_traps_F006_S002 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F006_S002_I000 | ||
| description: When an access fault exception is raised, the corresponding address | ||
| is stored into `mtval` CSR. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when any access fault exception is raised, `mtval` | ||
| CSR contains the address of the portion of the access causing the fault. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: ZERO_TVAL parameter value? | ||
| - 003_mtval_page: !Subfeature | ||
| name: 003_mtval_page | ||
| tag: VP_traps_F006_S003 | ||
| next_elt_id: 1 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F006_S003_I000 | ||
| description: When an page fault exception is raised, the corresponding address | ||
| is stored into `mtval` CSR. | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.16 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when any page fault exception is raised, `mtval` CSR | ||
| contains the address of the portion of the access causing the fault. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 56 | ||
| coverage_loc: '' | ||
| comments: ZERO_TVAL parameter value? Only with MMU support | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,67 @@ | ||
| !Feature | ||
| next_elt_id: 2 | ||
| name: Exception Priority | ||
| id: 7 | ||
| display_order: 7 | ||
| subfeatures: !!omap | ||
| - 000_exception priority: !Subfeature | ||
| name: 000_exception priority | ||
| tag: VP_traps_F007_S000 | ||
| next_elt_id: 2 | ||
| display_order: 0 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F007_S000_I000 | ||
| description: "Exceptions are of lower priority than all interrupts.\nException | ||
| priority (high to low)\n- code=0x3: Instruction address breakpoint\n- code=0xC, | ||
| 0x1: Instruction page fault, instruction access fault\n- code=0x2: Illegal | ||
| instruction\n- code=0x8, 0x9, 0xB: Environment call from U-mode, from S-mode, | ||
| from M-mode\n- code=0x3: Environment break\n- code=0x3: Load/store/AMO address | ||
| breakpoint\n- code=0xD, 0xF, 0x5, 0x7: Load page fault, store/AMO page fault, | ||
| load access fault, store/AMO access fault\n- code=0x4, 0x6: Load address | ||
| misaligned, store/AMO address misaligned" | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when raising an exception together with a lower priority | ||
| one the cause of the higher priority exception is written in `mcause` register. | ||
| pfc: -1 | ||
| test_type: 2 | ||
| cov_method: 0 | ||
| cores: 40 | ||
| coverage_loc: '' | ||
| comments: '' | ||
| - 001_exception priority embedded: !Subfeature | ||
| name: 001_exception priority embedded | ||
| tag: VP_traps_F007_S001 | ||
| next_elt_id: 1 | ||
| display_order: 1 | ||
| items: !!omap | ||
| - '000': !VerifItem | ||
| name: '000' | ||
| tag: VP_traps_F007_S001_I000 | ||
| description: "Exceptions are of lower priority than all interrupts.\nException | ||
| priority (high to low)\n- code=0x1: Instruction access fault\n- code=0x2: | ||
| Illegal instruction\n- code=0xB: Environment call from M-mode\n- code=0x5, | ||
| 0x7: Load access fault, store access fault\n- code=0x4, 0x6: Load address | ||
| misaligned, store address misaligned" | ||
| reqt_doc: Privileged Architecture Version 20211203, Chapter 3.1.15 | ||
| ref_mode: page | ||
| ref_page: '' | ||
| ref_section: '' | ||
| ref_viewer: firefox | ||
| verif_goals: Check that when raising an exception together with a lower priority | ||
| one the cause of the higher priority exception is written in `mcause` register. | ||
| pfc: -1 | ||
| test_type: -1 | ||
| cov_method: -1 | ||
| cores: 16 | ||
| coverage_loc: '' | ||
| comments: '' | ||
| vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' | ||
| io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' | ||
| config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' | ||
| ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' |
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Interruptions feature section is missing.