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Add the HPDcache as cache subsystem #1513
Add the HPDcache as cache subsystem #1513
Commits on Oct 13, 2023
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Add HPDcache (submodule) as a possible cache subsystem
Signed-off-by: Cesar Fuguet <[email protected]>
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cva6: fix cache subsystem generation label
Rename cache subsystem generation label Co-authored-by: Florian Zaruba <[email protected]> Signed-off-by: Cesar Fuguet <[email protected]>
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instr_tracer: prevent the synthesis of the instruction tracer
Signed-off-by: Cesar Fuguet <[email protected]>
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tb/ariane_testharness: compute AXI ID width into the ariane_axi_soc_pkg
All AXI related definitions are moved from the ariane_soc_pkg to the ariane_axi_soc_pkg. By computing the AXI ID width for slaves and masters of the crossbar in the ariane_axi_soc_pkg, widths can be correctly propagated from the CVA6 configuration package to the testbench. Signed-off-by: Cesar Fuguet <[email protected]>
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makefile: fix path to allow VCD tracing with Verilator
Signed-off-by: Cesar Fuguet <[email protected]>
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cva6: add labels to all cache subsystem generation statements
Co-authored-by: Nils Wistoff <[email protected]> Signed-off-by: Cesar Fuguet <[email protected]>
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hpdcache: use HTTPs URL for the hpdcache submodule
Signed-off-by: Cesar Fuguet <[email protected]>
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hpdcache: use short version of the SolderPad Licence header
Signed-off-by: Cesar Fuguet <[email protected]>
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hpdcache: add default HPDCache configuration package
Signed-off-by: Cesar Fuguet <[email protected]>
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verif: add HPDCACHE related variables in verif Makefile
Signed-off-by: Cesar Fuguet <[email protected]>
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Commits on Oct 14, 2023
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fpga: add script to generate a flatten Flist for FPGA synthesis
Signed-off-by: Cesar Fuguet <[email protected]>
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