ZiCond Extension #1262
ZiCond Extension #1262
Conversation
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✔️ successful run, report available here. |
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Great contribution @asimahsan1990 !! |
I propose to enable Zicond for 64 bits configuration
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As discussed during CVA6 verification meeting, I propose to enable Zicond for 64 bit configuration, the objective is to be able to use it on at least one CVA6 configuration. |
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❌ failed run, report available here. |
On Arch-test, there is PR open; those tests be available soon. Currently, there aren't any tests available that we can use. |
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Thank you @asimahsan1990 for making the required changes. It will be good to run the available tests (riscv-non-isa/riscv-arch-test#321) on CVA6 and check against spike (riscv-software-src/riscv-isa-sim#1241) and mention the test status in the PR description as well. |
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@JeanRochCoulon what we should do about the code coverage. |
This PR is for implementation of Zicond ratified v1.0 (conditional integer operations) extension. As for the verification, I have just verified at the unit level. Currently, Zicond is in progress on the GCC (a patch is available). On LLVM, it is available in the current version(17).
The "Conditional" operations extension provides a simple solution that provides most of the benefits and flexibility one would desire to support conditional arithmetic and conditional-select/move operations while remaining true to the RISC-V design philosophy. The instructions follow the format for R-type instructions with three operands (i.e., two source operands and one destination operand). Using these instructions, branch-less sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other micro-architectural provisions.