Replace WT_DCACHE define by CVA6ConfigCacheType localparam

.github/workflows/ci.yml

@@ -13,7 +13,7 @@ jobs:
     strategy:
       matrix:
         testcase: [asm-tests, mul, amo, fp, benchmarks]
-        cache: [WB_DCACHE, WT_DCACHE]
+        target: [cv64a6_imafdc_sv39, cv32a60x, cv32a6_imafc_sv32]
     env:
       RISCV: /riscv
     steps:

.gitlab-ci/cva6.yml

@@ -53,83 +53,83 @@ build:
 asm-quest:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-asm-tests batch-mode=1 defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-asm-tests batch-mode=1
   dependencies:
     - build
 
 amo-quest:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-amo-tests batch-mode=1 defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-amo-tests batch-mode=1
   dependencies:
     - build
 
 # floating point
 fp-quest:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-fp-tests batch-mode=1 defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-fp-tests batch-mode=1
   dependencies:
     - build
 
 bench-quest:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-benchmarks batch-mode=1 defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-benchmarks batch-mode=1
   dependencies:
     - build
 
 # rv64ui-p-* tests
 asm1-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-asm-tests1-verilator
   dependencies:
     - build
 
 # rv64ui-v-* tests
 asm2-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-asm-tests2-verilator
   dependencies:
     - build
 
 # rv64um-*-* tests
 mul-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-mul-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-mul-verilator
   dependencies:
     - build
 
 # atomics
 amo-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-amo-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-amo-verilator
   dependencies:
     - build
 
 # floating point
 fp-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-fp-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-fp-verilator
   dependencies:
     - build
 
 bench-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-benchmarks-verilator
   dependencies:
     - build
 
 bench-ver:
   stage: write-back
   script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
+    - make -j${NUM_JOBS} run-benchmarks-verilator
   dependencies:
     - build
 
@@ -150,108 +150,3 @@ serdiv-quest:
   dependencies:
     - build
 
-###################################
-# tests with write-through cache system
-
-s-asm-quest:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-asm-tests defines=WT_DCACHE batch-mode=1
-  dependencies:
-    - build
-
-# atomics
-s-amo-quest:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-amo-tests defines=WT_DCACHE batch-mode=1
-  dependencies:
-    - build
-
-# floating point
-s-fp-quest:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-fp-tests defines=WT_DCACHE batch-mode=1
-  dependencies:
-    - build
-
-s-bench-quest:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-benchmarks defines=WT_DCACHE batch-mode=1
-  dependencies:
-    - build
-
-# rv64ui-p-* tests
-s-asm1-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-# rv64ui-v-* tests
-s-asm2-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-# rv64um-*-* tests
-mul-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-mul-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-# atomics
-amo-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-amo-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-# floating point
-s-fp-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-fp-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-s-bench-ver:
-  stage: write-through
-  script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
-  dependencies:
-    - build
-
-s-icache-quest:
-  stage: write-through
-  script:
-    - cd tb/tb_icache/
-    - make simc
-    - "grep 'CI: PASSED' summary.rep"
-
-s-dcache-quest:
-  stage: write-through
-  script:
-    - cd tb/tb_wt_dcache/
-    - make simc
-    - "grep 'CI: PASSED' RD0_summary.rep"
-    - "grep 'CI: PASSED' RD1_summary.rep"
-    - "grep 'CI: PASSED' TB_MEM_summary.rep"
-  dependencies:
-    - build
-
-# s-torture:
-#   stage: write-through
-#   script:
-#     - make torture-rtest           defines=WT_DCACHE batch-mode=1
-#     - make torture-rtest-verilator defines=WT_DCACHE
-#   dependencies:
-#     - build

Bender.yml

@@ -20,9 +20,7 @@ dependencies:
 frozen: true
 
 sources:
-  - defines:
-      WT_DCACHE: 1
-    files:
+  - files:
       - target: cv64a6_imafdc_sv39
         files:
           - core/include/cv64a6_imafdc_sv39_config_pkg.sv

Makefile

@@ -29,7 +29,7 @@ verilator      ?= verilator
 # traget option
 target-options ?=
 # additional definess
-defines        ?= WT_DCACHE+RVFI_TRACE
+defines        ?= RVFI_TRACE
 # test name for torture runs (binary name)
 test-location  ?= output/test
 # set to either nothing or -log
@@ -282,7 +282,7 @@ endif
 vcs_build: $(dpi-library)/ariane_dpi.so
 	mkdir -p $(vcs-library)
 	cd $(vcs-library) &&\
-	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -f ../core/Flist.cva6 &&\
+	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
 	vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../vendor/pulp-platform/common_cells/include/+../vendor/pulp-platform/axi/include/+../corev_apu/register_interface/include/ &&\

README.md

@@ -328,7 +328,7 @@ CVA6 has preliminary support for the OpenPiton distributed cache system from Pri
 
 The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use CVA6 in the OpenPiton setting.
 
-To activate the different cache system, compile your code with the macro `WT_DCACHE` (set by default).
+To activate the different cache system, compile your code with the macro `DCACHE_TYPE`.
 
 ## Planned Improvements
 

core/Flist.cva6

@@ -25,8 +25,6 @@
 //
 ///////////////////////////////////////////////////////////////////////////////
 
-+define+WT_DCACHE
-
 //FPGA memories
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
@@ -62,6 +60,11 @@ ${CVA6_REPO_DIR}/core/cvxif_example/instr_decoder.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_mux.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_demux.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
@@ -146,6 +149,13 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/tag_cmp.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/axi_adapter.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/miss_handler.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/cache_ctrl.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache_axi_wrapper.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/std_cache_subsystem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/std_nbdcache.sv
 
 // Physical Memory Protection
 // NOTE: pmp.sv modified for DSIM (unchanged for other simulators)