Incorrect documentation of mtvec CSR in user manual

[spidugu444]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

This issue points out mtvec documentation.
In CVA6 CSR documentation, Mode field access for mtvec is mentioned as RW as shown below.

Bits	Name	Display Name	Access Type	Reset
[31:2]	BASE		RW	0b0
[1:0]	MODE		RW	0b0

The access type for the Mode field should be as mentioned below.

As per the CVA6 for mtvec CSR mode field we have two implementation options i.e Direct Mode(00) and vector Mode (01).so the mode[1] bit is fixed to 0 making this bit to RO.

Bits	Mode	Description
1	RO	MODE[1]: always 0
0	RW	MODE[0]: 0 = direct mode, 1 = vectored mode.

[JeanRochCoulon]

Thank you @spidugu444 for this GitHub issue.
As it is connected with the previous discussion involving @ASintzoff and @MikeOpenHWGroup about #1049, I prefer to have it assigned to André

[MikeOpenHWGroup]

Hi @JeanRochCoulon. It is good that you have an opinion about who to assign this to. In such cases, please feel free to change the Assignee.

Hi @spidugu444. Please ensure that Component and Status flags are added to each Issue.