Making CORE-V safe for the world to use.
Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.
- Ottawa, Ontario, Canada
- http://www.openhwgroup.org
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riscv-dv
riscv-dv PublicForked from chipsalliance/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
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openhwgroup/cv32e40p
openhwgroup/cv32e40p PublicCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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openhwgroup/core-v-verif
openhwgroup/core-v-verif PublicFunctional verification project for the CORE-V family of RISC-V cores.
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openhwgroup/programs
openhwgroup/programs PublicDocumentation for the OpenHW Group's set of CORE-V RISC-V cores
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