Merge branch 'master' into how_to_design_a_coprocessor

.gitlab-ci.yml

@@ -135,7 +135,23 @@ build_tools:
   - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
   - if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
 
-smoke:
+smoke-tests-cv32a65x:
+  extends:
+    - .fe_smoke_test
+  variables:
+    DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
+    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Basic"
+    SPIKE_TANDEM: 1
+    COLLECT_SIMU_LOGS: 1
+    DV_SIMULATORS: "vcs-uvm"
+  script:
+    - bash verif/regress/smoke-tests-cv32a65x.sh
+    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
+    - !reference [.simu_after_script]
+
+smoke-tests-cv32a6_imac_sv32:
   extends:
     - .fe_smoke_test
   variables:
@@ -148,17 +164,36 @@ smoke:
   parallel:
     matrix:
       - DV_SIMULATORS:
-        - "veri-testharness,spike"
         - "vcs-testharness"
-        - "questa-testharness,spike"
-        - "vcs-uvm"
+        - "questa-testharness"
   script:
     - source $QUESTA_BASHRC
-    - bash verif/regress/smoke-tests.sh
+    - bash verif/regress/smoke-tests-cv32a6_imac_sv32.sh
     - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
     - !reference [.simu_after_script]
 
-gen_smoke:
+smoke-tests-cv64a6_imafdc_sv39:
+  extends:
+    - .fe_smoke_test
+  variables:
+    DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
+    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Basic"
+    SPIKE_TANDEM: 1
+    COLLECT_SIMU_LOGS: 1
+  parallel:
+    matrix:
+      - DV_SIMULATORS:
+        - "vcs-testharness"
+        - "questa-testharness"
+  script:
+    - source $QUESTA_BASHRC
+    - bash verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh
+    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
+    - !reference [.simu_after_script]
+
+smoke-gen:
   extends:
     - .fe_smoke_test
   variables:
@@ -173,28 +208,32 @@ gen_smoke:
     - bash verif/regress/smoke-gen_tests.sh
     - !reference [.simu_after_script]
 
-coremark:
+smoke-bench:
   extends:
     - .fe_smoke_test
   variables:
-    DASHBOARD_JOB_TITLE: "CoreMark"
+    DASHBOARD_JOB_TITLE: "smoke-bench"
     DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Performance"
+    SPIKE_TANDEM: 1
+    BENCH: "dhrystone"
   script:
-    - bash verif/regress/coremark.sh --no-print
-    - python3 .gitlab-ci/scripts/report_benchmark.py --coremark verif/sim/out_*/veri-testharness_sim/core_main.*.log
+    - bash verif/regress/"$BENCH"_smoke.sh --no-print
+    - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_cv32a65x verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
 
-hwconfig:
+smoke-hwconfig:
   extends:
     - .fe_smoke_test
   variables:
     DASHBOARD_JOB_TITLE: "HW config $DV_SIMULATORS $DV_HWCONFIG_OPTS"
     DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations"
     DASHBOARD_SORT_INDEX: 1
     DASHBOARD_JOB_CATEGORY: "Basic"
-    DV_SIMULATORS: "veri-testharness,spike"
-    DV_HWCONFIG_OPTS: "cv32a6_imac_sv32"
+    DV_SIMULATORS: "vcs-uvm"
+    SPIKE_TANDEM: 1
+    DV_TARGET: "hwconfig"
+    DV_HWCONFIG_OPTS: "cv32a65x"
   script:
     - source verif/regress/hwconfig_tests.sh
     - python3 .gitlab-ci/scripts/report_pass.py
@@ -268,7 +307,7 @@ asic-synthesis:
     - echo $PERIOD
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -309,17 +348,32 @@ fpga-build:
     - when: manual
       allow_failure: true
 
-dhrystone:
+benchmarks:
   extends:
     - .regress_test
   variables:
-    DASHBOARD_JOB_TITLE: "Dhrystone"
+    DASHBOARD_JOB_TITLE: "benchmarks"
     DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Performance"
+    SPIKE_TANDEM: 1
+  parallel:
+    matrix:
+      - BENCH: "dhrystone"
+        ISSUE: "single"
+        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+      - BENCH: "dhrystone"
+        ISSUE: "dual"
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+      - BENCH: "coremark"
+        ISSUE: "single"
+        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+      - BENCH: "coremark"
+        ISSUE: "dual"
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
   script:
-    - bash verif/regress/dhrystone.sh
-    - python3 .gitlab-ci/scripts/report_benchmark.py --dhrystone verif/sim/out_*/veri-testharness_sim/dhrystone_main.*.log
+    - bash verif/regress/"$BENCH".sh
+    - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
 
 riscv_arch_test:
   extends:
@@ -348,16 +402,18 @@ compliance:
   after_script: *simu_after_script
 
 riscv-tests-v:
+  timeout : 2 hours
   extends:
     - .regress_test
   variables:
     DASHBOARD_JOB_TITLE: "Riscv-test $DV_TARGET (virtual)"
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
     DASHBOARD_SORT_INDEX: 3
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness,spike"
     DV_TARGET: cv64a6_imafdc_sv39
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-tests.sh
   after_script: *simu_after_script
 
@@ -505,19 +561,21 @@ simu-gate:
     matrix:
       - SIMU_PERIOD: ["20"]  # 50 Mhz
         PERIOD:      ["15"]  # 66 Mhz
+        PROG_NAME:   "dhrystone"
   variables:
     DASHBOARD_JOB_TITLE: "Gate Level Simulation $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Tests to check netlist from ASIC synthesis and power consumption over different patterns"
     DASHBOARD_SORT_INDEX: 6
     DASHBOARD_JOB_CATEGORY: "Post Synthesis"
     DV_TARGET: cv32a65x
     TARGET: $DV_TARGET
+    SPIKE_TANDEM: 1
   script:
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
@@ -527,6 +585,7 @@ simu-gate:
     - mkdir -p pd/synth/cva6_${DV_TARGET}/outputs/
     - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=$PROG_NAME
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
+    - rm artifacts/artifacts_gate/*/build/*.fsdb
   after_script: *simu_after_script
 
 fpga-boot:

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 172749
+  gates: 176232

.gitlab-ci/scripts/report_benchmark.py

@@ -7,7 +7,9 @@
 #
 # Original Author: Côme Allart
 
+import os
 import sys
+import re
 import report_builder as rb
 
 path = None
@@ -17,54 +19,56 @@
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    'dhrystone': 215902,
-    'coremark': 534419,
+    "dhrystone_dual": 20199,
+    "dhrystone_single": 25019,
+    "coremark_dual": 1017451,
+    "coremark_single": 1308656,
+    "dhrystone_cv32a65x": 32566,
 }
 
 for arg in sys.argv[1:]:
-    if arg == '--dhrystone':
-        mode = 'dhrystone'
-        # Standard value for Dhrystone
-        iterations = 500
-    elif arg == '--coremark':
-        mode = 'coremark'
-        # Defined in verif/regress/coremark.sh
-        iterations = 2
+    if "--dhrystone" in arg or "--coremark" in arg:
+        if "--dhrystone" in arg:
+            iterations = 50
+        else:
+            if "--coremark" in arg:
+                iterations = 4
+        mode = arg.replace("-", "")
     else:
         path = arg
 
 # We do not want to have a report without a check
 assert mode is not None
 
-with open(path, 'r') as f:
+with open(path, "r") as f:
     log = [l.strip() for l in f.readlines()]
 
 stopwatch = []
 for index, line in enumerate(log):
-    if line.split()[-1] == 'mcycle' or line.split()[-2] == 'mcycle,':
+    if line.split()[-1] == "mcycle" or line.split()[-2] == "mcycle,":
         stopwatch.append(int(log[index + 1].split()[-1], 16))
 # There might be > 2 matches, we use the two at the center
 N = len(stopwatch)
 assert N % 2 == 0
-cycles = stopwatch[N//2] - stopwatch[N//2-1]
+cycles = stopwatch[N // 2] - stopwatch[N // 2 - 1]
 
-score_metric = rb.TableMetric('Performance results')
-score_metric.add_value('cycles', cycles)
+score_metric = rb.TableMetric("Performance results")
+score_metric.add_value("cycles", cycles)
 
 if iterations is not None:
     ipmhz = iterations * 1000000 / cycles
-    if mode == 'dhrystone':
-        score_metric.add_value('Dhrystone/MHz', ipmhz)
-        score_metric.add_value('DMIPS/MHz', ipmhz / 1757)
-    if mode == 'coremark':
-        score_metric.add_value('CoreMark/MHz', ipmhz)
+    if "dhrystone" in mode:
+        score_metric.add_value("Dhrystone/MHz", ipmhz)
+        score_metric.add_value("DMIPS/MHz", ipmhz / 1757)
+    if "coremark" in mode:
+        score_metric.add_value("CoreMark/MHz", ipmhz)
 
 diff = cycles - valid_cycles[mode]
 if diff != 0:
     score_metric.fail()
-    score_metric.add_value('Cycles diff', diff)
+    score_metric.add_value("Cycles diff", diff)
 
-report = rb.Report(f'{cycles//1000} kCycles')
+report = rb.Report(f"{cycles//1000} kCycles")
 report.add_metric(score_metric)
 report.dump()
 

.gitlab-ci/scripts/report_builder.py

@@ -172,12 +172,19 @@ def to_doc(self):
 
     def dump(self, path=None):
         """
-        Create report file
+        Print results and create report file
 
         By default the output path is build from $CI_JOB_NAME
         """
+        for metric in self.metrics:
+            print(metric.values)
+
         if path is None:
-            filename = re.sub(r'[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"])
-            path = 'artifacts/reports/'+filename+'.yml'
-        with open(path, 'w') as f:
-            yaml.dump(self.to_doc(), f)
+            ci_job_name = os.environ.get("CI_JOB_NAME")
+            if ci_job_name is not None:
+                filename = re.sub(r'[^\w\.\\\/]', '_', ci_job_name)
+                path = 'artifacts/reports/'+filename+'.yml'
+
+        if path is not None:
+            with open(path, 'w') as f:
+                yaml.dump(self.to_doc(), f)

.readthedocs.yaml

@@ -8,6 +8,14 @@ build:
   os: "ubuntu-20.04"
   tools:
     python: "3.9"
+    nodejs: "20"
+    ruby: "3.3"
+  jobs:
+    post-install:
+      - npm install docs/riscv-isa/riscv-isa-manual/dependencies
+      - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile
+    pre-build:
+      - make -C docs prepare
 
 # Build from the docs directory with Sphinx
 sphinx:

README.md

@@ -97,7 +97,7 @@ cd ./verif/sim
 
 python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \
 --c_tests ../tests/custom/hello_world/hello_world.c \
---linker=../tests/custom/common/test.ld \
+--linker=../../config/gen_from_riscv_config/linker/link.ld \
 --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \
 -nostartfiles -g ../tests/custom/common/syscalls.c \
 ../tests/custom/common/crt.S -lgcc \
@@ -417,6 +417,10 @@ If you use CVA6 in your academic work you can cite us:
 <br/>
 
 
+# Resources and Ecosystem
+
+The CVA6 core is part of a vivid ecosystem. In [this document](RESOURCES.md), we gather pointers to this ecosystem (building blocks, designs, partners...)
+
 # Acknowledgements
 
 Check out the [acknowledgements](ACKNOWLEDGEMENTS.md).