doc: clarify mtval register description when not enabled (#2271)

openhwgroup · Jun 19, 2024 · 89568b0 · 89568b0
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diff --git a/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html b/docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html
@@ -3972,7 +3972,8 @@ <h4 id="mcause">3.1.15. Machine Cause (<code>mcause</code>) Register</h4>
 <div class="sect3">
 <h4 id="_machine_trap_value_mtval_register">3.1.16. Machine Trap Value (<code>mtval</code>) Register</h4>
 <div class="paragraph">
-<p>[CV32A65X] The <code>mtval</code> register is an MXLEN-bit read-only 0 register.</p>
+<p>[CV32A65X] The <code>mtval</code> register is an MXLEN-bit read-write register
+holding constant value zero.</p>
 </div>
 </div>
 <div class="sect3">

diff --git a/docs/riscv-isa/src/machine.adoc b/docs/riscv-isa/src/machine.adoc
@@ -2553,7 +2553,8 @@ _N_ is the smaller of MXLEN and ILEN.
 endif::[]
 
 ifeval::[{MTvalEn} == false]
-[{ohg-config}] The `mtval` register is an MXLEN-bit read-only 0 register.
+[{ohg-config}] The `mtval` register is an MXLEN-bit read-write register
+holding constant value zero.
 endif::[]
 
 ==== Machine Configuration Pointer (`mconfigptr`) Register