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[bot]: Add stale-bot
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zarubaf committed Oct 19, 2023
1 parent d2d178d commit 7814c02
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4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
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Expand Up @@ -22,5 +22,5 @@ jobs:
submodules: recursive
- name: Prepare
run: ci/setup.sh
- name: run tests
run: make run-${{ matrix.testcase}}-verilator target=${{ matrix.target }}
# - name: run tests
# run: make run-${{ matrix.testcase}}-verilator target=${{ matrix.target }}
32 changes: 32 additions & 0 deletions .github/workflows/stale.yml
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@@ -0,0 +1,32 @@
# Copyright 2023 OpenHW Group
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

name: 'Close stale issues and PRs'
# on:
# schedule:
# - cron: '30 1 * * *'
on: workflow_dispatch

jobs:
stale:
runs-on: ubuntu-latest
steps:
- uses: actions/stale@v8
with:
debug-only: true
stale-issue-label: Status:Stale
stale-pr-label: Status:Stale
stale-issue-message: |
👋 Hi there!
This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊
stale-pr-message: |
👋 Hi there!
This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊
days-before-stale: 30
days-before-close: 5
exempt-issue-labels: Type:Task,Type:Enhancement,Type:Bug
exempt-all-milestones: true
start-date: '2023-09-01T00:00:00Z'
2 changes: 1 addition & 1 deletion corev_apu/axi_mem_if
2 changes: 1 addition & 1 deletion corev_apu/register_interface
Submodule register_interface updated 88 files
+0 −16 .github/verible-lint-matcher.json
+0 −58 .github/workflows/lint.yml
+0 −2 .gitignore
+4 −20 Bender.yml
+2 −37 CHANGELOG.md
+0 −176 LICENSE
+1 −11 README.md
+0 −46 include/register_interface/assign.svh
+0 −38 include/register_interface/typedef.svh
+0 −6 ips_list.yml
+0 −10 lint/verible.waiver
+32 −112 src/axi_lite_to_reg.sv
+4 −109 src/axi_to_reg.sv
+0 −105 src/periph_to_reg.sv
+0 −177 src/reg_cdc.sv
+0 −37 src/reg_demux.sv
+56 −0 src/reg_intf_pkg.sv
+0 −71 src/reg_mux.sv
+0 −58 src/reg_to_mem.sv
+11 −11 src/reg_uniform.sv
+0 −49 src_files.yml
+0 −774 util/vendor.py
+0 −14 vendor/lowrisc_opentitan.lock.hjson
+0 −25 vendor/lowrisc_opentitan.vendor.hjson
+0 −64 vendor/lowrisc_opentitan/src/prim_subreg.sv
+0 −79 vendor/lowrisc_opentitan/src/prim_subreg_arb.sv
+0 −28 vendor/lowrisc_opentitan/src/prim_subreg_ext.sv
+0 −157 vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv
+0 −113 vendor/lowrisc_opentitan/util/reggen/README.md
+0 −0 vendor/lowrisc_opentitan/util/reggen/__init__.py
+0 −121 vendor/lowrisc_opentitan/util/reggen/access.py
+0 −54 vendor/lowrisc_opentitan/util/reggen/alert.py
+0 −87 vendor/lowrisc_opentitan/util/reggen/bits.py
+0 −187 vendor/lowrisc_opentitan/util/reggen/bus_interfaces.py
+0 −35 vendor/lowrisc_opentitan/util/reggen/enum_entry.py
+0 −291 vendor/lowrisc_opentitan/util/reggen/field.py
+0 −177 vendor/lowrisc_opentitan/util/reggen/fpv_csr.sv.tpl
+0 −113 vendor/lowrisc_opentitan/util/reggen/gen_cfg_html.py
+0 −439 vendor/lowrisc_opentitan/util/reggen/gen_cheader.py
+0 −108 vendor/lowrisc_opentitan/util/reggen/gen_dv.py
+0 −81 vendor/lowrisc_opentitan/util/reggen/gen_fpv.py
+0 −325 vendor/lowrisc_opentitan/util/reggen/gen_html.py
+0 −34 vendor/lowrisc_opentitan/util/reggen/gen_json.py
+0 −136 vendor/lowrisc_opentitan/util/reggen/gen_rtl.py
+0 −306 vendor/lowrisc_opentitan/util/reggen/gen_selfdoc.py
+0 −83 vendor/lowrisc_opentitan/util/reggen/html_helpers.py
+0 −81 vendor/lowrisc_opentitan/util/reggen/inter_signal.py
+0 −365 vendor/lowrisc_opentitan/util/reggen/ip_block.py
+0 −262 vendor/lowrisc_opentitan/util/reggen/lib.py
+0 −142 vendor/lowrisc_opentitan/util/reggen/multi_register.py
+0 −341 vendor/lowrisc_opentitan/util/reggen/params.py
+0 −45 vendor/lowrisc_opentitan/util/reggen/reg_base.py
+0 −431 vendor/lowrisc_opentitan/util/reggen/reg_block.py
+0 −74 vendor/lowrisc_opentitan/util/reggen/reg_html.css
+0 −347 vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
+0 −712 vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
+0 −375 vendor/lowrisc_opentitan/util/reggen/register.py
+0 −63 vendor/lowrisc_opentitan/util/reggen/signal.py
+0 −14 vendor/lowrisc_opentitan/util/reggen/uvm_reg.sv.tpl
+0 −431 vendor/lowrisc_opentitan/util/reggen/uvm_reg_base.sv.tpl
+0 −155 vendor/lowrisc_opentitan/util/reggen/validate.py
+0 −24 vendor/lowrisc_opentitan/util/reggen/version.py
+0 −169 vendor/lowrisc_opentitan/util/reggen/window.py
+0 −235 vendor/lowrisc_opentitan/util/regtool.py
+0 −8 vendor/lowrisc_opentitan/util/topgen/__init__.py
+0 −444 vendor/lowrisc_opentitan/util/topgen/c.py
+0 −46 vendor/lowrisc_opentitan/util/topgen/gen_dv.py
+0 −1,005 vendor/lowrisc_opentitan/util/topgen/intermodule.py
+0 −497 vendor/lowrisc_opentitan/util/topgen/lib.py
+0 −1,081 vendor/lowrisc_opentitan/util/topgen/merge.py
+0 −4 vendor/lowrisc_opentitan/util/topgen/templates/README.md
+0 −17 vendor/lowrisc_opentitan/util/topgen/templates/chip_env_pkg__params.sv.tpl
+0 −1,218 vendor/lowrisc_opentitan/util/topgen/templates/chiplevel.sv.tpl
+0 −4 vendor/lowrisc_opentitan/util/topgen/templates/clang-format
+0 −21 vendor/lowrisc_opentitan/util/topgen/templates/tb__alert_handler_connect.sv.tpl
+0 −124 vendor/lowrisc_opentitan/util/topgen/templates/tb__xbar_connect.sv.tpl
+0 −21 vendor/lowrisc_opentitan/util/topgen/templates/toplevel.c.tpl
+0 −201 vendor/lowrisc_opentitan/util/topgen/templates/toplevel.h.tpl
+0 −832 vendor/lowrisc_opentitan/util/topgen/templates/toplevel.sv.tpl
+0 −62 vendor/lowrisc_opentitan/util/topgen/templates/toplevel_memory.h.tpl
+0 −30 vendor/lowrisc_opentitan/util/topgen/templates/toplevel_memory.ld.tpl
+0 −112 vendor/lowrisc_opentitan/util/topgen/templates/toplevel_pkg.sv.tpl
+0 −44 vendor/lowrisc_opentitan/util/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl
+0 −88 vendor/lowrisc_opentitan/util/topgen/templates/xbar_env_pkg__params.sv.tpl
+0 −122 vendor/lowrisc_opentitan/util/topgen/top.py
+0 −151 vendor/lowrisc_opentitan/util/topgen/top_uvm_reg.sv.tpl
+0 −878 vendor/lowrisc_opentitan/util/topgen/validate.py
+0 −386 vendor/patches/lowrisc_opentitan/0001-Add-reg_interface-support.patch
2 changes: 1 addition & 1 deletion corev_apu/rv_plic

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