Adding Fields VS and UBE to MSTATUS in Specification to solve issue #…

…1131 (#1308) Co-authored-by: Frikha Mohamed Aziz <[email protected]>
openhwgroup · Jul 19, 2023 · 5fff224 · 5fff224
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diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.md b/docs/01_cva6_user/ip-xact/cva6_csr.md
@@ -199,8 +199,10 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
 | 16:15 | XS | Extension state | read-only  | The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\.  This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) |
 | 14:13 | FS | Floating-point unit state | read-write  | The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\.  This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) |
 | 12:11 | MPP | Machine mode prior privilege | read-write  | Holds the previous privilege mode for machine mode\.|
+| 10:9 | VS | Vector extension state | read-only  | V extension is not supported VS=0\.|
 | 8 | SPP | Supervisor mode prior privilege | read-write  | Holds the previous privilege mode for supervisor mode\.|
 | 7 | MPIE | Machine mode prior interrupt enable | read-write  | Indicates whether machine interrupts were enabled prior to trapping into machine mode\.|
+| 6 | UBE | User breakpoint enable | read-write  | UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian \(UBE=0\) or big\-endian \(UBE=1\)\.|
 | 5 | SPIE | Supervisor mode prior interrupt enable | read-write  | Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\.|
 | 4 | WPRI2 | Reserved writes preserve values, reads ignore value | read-write  | Reserved Writes Preserve Values, Reads Ignore Value|
 | 3 | MIE | Machine mode interrupt enable | read-write  | Global interrupt\-enable bit for Machine mode\.|

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.rst b/docs/01_cva6_user/ip-xact/cva6_csr.rst
@@ -652,6 +652,11 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
      - Machine mode prior privilege
      - read-write
      - Holds the previous privilege mode for machine mode\.
+   * - 10:9
+     - VS
+     - Vector extension state
+     - read-only
+     - V extension is not supported VS=0\.
    * - 8 
      - SPP
      - Supervisor mode prior privilege
@@ -662,6 +667,11 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat
      - Machine mode prior interrupt enable
      - read-write
      - Indicates whether machine interrupts were enabled prior to trapping into machine mode\.
+   * - 6 
+     - UBE
+     - User breakpoint enable 
+     - read-write
+     - UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian \(UBE=0\) or big\-endian \(UBE=1\)\.
    * - 5 
      - SPIE
      - Supervisor mode prior interrupt enable

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.xml b/docs/01_cva6_user/ip-xact/cva6_csr.xml
@@ -1352,6 +1352,23 @@ This field can be checked by a context switch routine to quickly determine wheth
                                                 <ipxact:bitWidth>2</ipxact:bitWidth>
                                                 <ipxact:access>read-write</ipxact:access>
                                         </ipxact:field>
+                                        <ipxact:field>
+                                                <ipxact:name>VS</ipxact:name>
+                                                <ipxact:displayName>Vector extension State</ipxact:displayName>
+                                                <ipxact:description>V extension is not supported VS=0.</ipxact:description>
+                                                <ipxact:bitOffset>9</ipxact:bitOffset>
+                                                <ipxact:resets>
+                                                        <ipxact:reset>
+                                                                <ipxact:value>0x0</ipxact:value>
+                                                                <ipxact:mask>0x3</ipxact:mask>
+                                                        </ipxact:reset>
+                                                </ipxact:resets>
+                                                <ipxact:bitWidth>2</ipxact:bitWidth>
+                                                <ipxact:access>read-only</ipxact:access>
+                                                <ipxact:vendorExtensions>
+                                                        <RISCV_behavior>WARL</RISCV_behavior>
+                                                </ipxact:vendorExtensions>
+                                        </ipxact:field>
                                         <ipxact:field>
                                                 <ipxact:name>SPP</ipxact:name>
                                                 <ipxact:displayName>Supervisor mode Prior Privilege</ipxact:displayName>
@@ -1380,6 +1397,23 @@ This field can be checked by a context switch routine to quickly determine wheth
                                                 <ipxact:bitWidth>1</ipxact:bitWidth>
                                                 <ipxact:access>read-write</ipxact:access>
                                         </ipxact:field>
+                                        <ipxact:field>
+                                                <ipxact:name>UBE</ipxact:name>
+                                                <ipxact:displayName>User Breakpoint Enable</ipxact:displayName>
+                                                <ipxact:description>UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).</ipxact:description>
+                                                <ipxact:bitOffset>6</ipxact:bitOffset>
+                                                <ipxact:resets>
+                                                        <ipxact:reset>
+                                                                <ipxact:value>0x0</ipxact:value>
+                                                                <ipxact:mask>0x1</ipxact:mask>
+                                                        </ipxact:reset>
+                                                </ipxact:resets>
+                                                <ipxact:bitWidth>1</ipxact:bitWidth>
+                                                <ipxact:access>read-write</ipxact:access>
+                                                <ipxact:vendorExtensions>
+                                                        <RISCV_behavior>WARL</RISCV_behavior>
+                                                </ipxact:vendorExtensions>
+                                        </ipxact:field>
                                         <ipxact:field>
                                                 <ipxact:name>SPIE</ipxact:name>
                                                 <ipxact:displayName>Supervisor mode Prior Interrupt Enable</ipxact:displayName>

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.yaml b/docs/01_cva6_user/ip-xact/cva6_csr.yaml
@@ -958,6 +958,18 @@ component:
                 mask: '0x3'
             bitWidth: '2'
             access: read-write
+          - name: VS
+            displayName: Vector extension State
+            description: V extension is not supported VS=0.
+            bitOffset: '9'
+            resets:
+              reset:
+                value: '0x0'
+                mask: '0x3'
+            bitWidth: '2'
+            access: read-only
+            vendorExtensions:
+              RISCV_behavior: WARL
           - name: SPP
             displayName: Supervisor mode Prior Privilege
             description: Holds the previous privilege mode for supervisor mode.
@@ -978,6 +990,18 @@ component:
                 mask: '0x1'
             bitWidth: '1'
             access: read-write
+          - name: UBE
+            displayName: User Breakpoint Enable
+            description: UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).
+            bitOffset: '6'
+            resets:
+              reset:
+                value: '0x0'
+                mask: '0x1'
+            bitWidth: '1'
+            access: read-write
+            vendorExtensions:
+              RISCV_behavior: WARL
           - name: SPIE
             displayName: Supervisor mode Prior Interrupt Enable
             description: Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.