resolving lint warnings... (#1529)

core/alu.sv

@@ -42,6 +42,7 @@ module alu
   logic [$clog2(riscv::XLEN)-1 : 0] lz_tz_count;  // Count Leading Zeros
   logic [                      4:0] lz_tz_wcount;  // Count Leading Zeros Word
   logic lz_tz_empty, lz_tz_wempty;
+  riscv::xlen_t orcbw_result, rev8w_result;
 
   // bit reverse operand_a for left shifts and bit counting
   generate
@@ -219,6 +220,18 @@ module alu
     );
   end
 
+  if (ariane_pkg::BITMANIP) begin : gen_orcbw_rev8w_results
+    assign orcbw = {{8{|fu_data_i.operand_a[31:24]}}, {8{|fu_data_i.operand_a[23:16]}}, {8{|fu_data_i.operand_a[15:8]}}, {8{|fu_data_i.operand_a[7:0]}}};
+    assign rev8w = {{fu_data_i.operand_a[7:0]}, {fu_data_i.operand_a[15:8]}, {fu_data_i.operand_a[23:16]}, {fu_data_i.operand_a[31:24]}};
+    if (riscv::XLEN == 64) begin : gen_64b
+      assign orcbw_result = {{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw};
+      assign rev8w_result = {rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}};
+    end else begin : gen_32b
+      assign orcbw_result = orcbw;
+      assign rev8w_result = rev8w;
+    end
+  end
+
   // -----------
   // Result MUX
   // -----------
@@ -249,18 +262,6 @@ module alu
     if (ariane_pkg::BITMANIP) begin
       // Index for Bitwise Rotation
       bit_indx = 1 << (fu_data_i.operand_b & (riscv::XLEN - 1));
-      orcbw = {
-        {8{|fu_data_i.operand_a[31:24]}},
-        {8{|fu_data_i.operand_a[23:16]}},
-        {8{|fu_data_i.operand_a[15:8]}},
-        {8{|fu_data_i.operand_a[7:0]}}
-      };
-      rev8w = {
-        {fu_data_i.operand_a[7:0]},
-        {fu_data_i.operand_a[15:8]},
-        {fu_data_i.operand_a[23:16]},
-        {fu_data_i.operand_a[31:24]}
-      };
       // rolw, roriw, rorw
       rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
       rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
@@ -302,9 +303,9 @@ module alu
         result_o = (riscv::XLEN == 64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
         RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
         ORCB:
-        result_o = (riscv::XLEN == 64) ? ({{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw}) : orcbw;
+        result_o = orcbw_result;
         REV8:
-        result_o = (riscv::XLEN == 64) ? ({rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}}) : rev8w;
+        result_o = rev8w_result;
 
         default: ;  // default case to suppress unique warning
       endcase

core/cache_subsystem/axi_adapter.sv

@@ -359,7 +359,7 @@ module axi_adapter #(
             if (amo_q == ariane_pkg::AMO_SC) begin
               if (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY) begin
                 // success -> return 0
-                rdata_o = 1'b0;
+                rdata_o = 'b0;
               end else begin
                 // failure -> when request is 64-bit, return 1;
                 // when request is 32-bit place a 1 in both upper

core/cache_subsystem/cva6_icache.sv

@@ -128,7 +128,7 @@ module cva6_icache
 
   // noncacheable if request goes to I/O space, or if cache is disabled
   assign paddr_is_nc = (~cache_en_q) | (~config_pkg::is_inside_cacheable_regions(
-      CVA6Cfg, {{{64 - riscv::PLEN} {1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}
+      CVA6Cfg, {{64 - riscv::PLEN{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}
   ));
 
   // pass exception through
@@ -176,7 +176,7 @@ module cva6_icache
   // main control logic
   ///////////////////////////////////////////////////////
   logic addr_ni;
-  assign addr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, areq_i.fetch_paddr);
+  assign addr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{64-riscv::PLEN{1'b0}}, areq_i.fetch_paddr});
   always_comb begin : p_fsm
     // default assignment
     state_d = state_q;

core/cache_subsystem/wt_dcache_ctrl.sv

@@ -97,7 +97,7 @@ module wt_dcache_ctrl
   // to miss unit
   assign miss_vld_bits_o = vld_data_q;
   assign miss_paddr_o = {address_tag_q, address_idx_q, address_off_q};
-  assign miss_size_o = (miss_nc_o) ? data_size_q : 3'b111;
+  assign miss_size_o = (miss_nc_o) ? {1'b0, data_size_q} : 3'b111;
 
   // noncacheable if request goes to I/O space, or if cache is disabled
   assign miss_nc_o = (~cache_en_i) | (~config_pkg::is_inside_cacheable_regions(

core/cache_subsystem/wt_dcache_mem.sv

@@ -239,7 +239,7 @@ module wt_dcache_mem
   end
 
   for (genvar k = 0; k < DCACHE_WBUF_DEPTH; k++) begin : gen_wbuffer_hit
-    assign wbuffer_hit_oh[k] = (|wbuffer_data_i[k].valid) & (wbuffer_data_i[k].wtag == (wbuffer_cmp_addr >> riscv::XLEN_ALIGN_BYTES));
+    assign wbuffer_hit_oh[k] = (|wbuffer_data_i[k].valid) & ({{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_data_i[k].wtag} == (wbuffer_cmp_addr >> riscv::XLEN_ALIGN_BYTES));
   end
 
   lzc #(
@@ -265,7 +265,7 @@ module wt_dcache_mem
   if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
     // In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
     assign wr_cl_off     = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
-                              wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] :
+                              {{DCACHE_OFFSET_WIDTH-AXI_OFFSET_WIDTH{1'b0}}, wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES]} :
                               wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES];
   end else begin : gen_piton_offset
     assign wr_cl_off = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];

core/cache_subsystem/wt_dcache_missunit.sv

@@ -138,8 +138,8 @@ module wt_dcache_missunit
   logic amo_sel, miss_is_write;
   logic amo_req_d, amo_req_q;
   logic [63:0] amo_rtrn_mux;
-  riscv::xlen_t amo_data;
-  logic [63:0] amo_user;  //DCACHE USER ? DATA_USER_WIDTH
+  riscv::xlen_t amo_data, amo_data_a, amo_data_b;
+  riscv::xlen_t amo_user;  //DCACHE USER ? DATA_USER_WIDTH
   logic [riscv::PLEN-1:0] tmp_paddr;
   logic [$clog2(NumPorts)-1:0] miss_port_idx;
   logic [DCACHE_CL_IDX_WIDTH-1:0] cnt_d, cnt_q;
@@ -242,53 +242,63 @@ module wt_dcache_missunit
   ///////////////////////////////////////////////////////
 
   // if size = 32bit word, select appropriate offset, replicate for openpiton...
-  always_comb begin
-    if (CVA6Cfg.RVA) begin
-       if (riscv::IS_XLEN64) begin
-         if (amo_req_i.size==2'b10) begin
-           amo_data = {amo_req_i.operand_b[0 +: 32], amo_req_i.operand_b[0 +: 32]};
-         end else begin
-           amo_data = amo_req_i.operand_b;
-         end
-       end else begin
-         amo_data = amo_req_i.operand_b[0 +: 32];
-       end
-       if (ariane_pkg::DATA_USER_EN) begin
-         amo_user = amo_data;
-       end else begin
-         amo_user = '0;
-       end
+
+  if (CVA6Cfg.RVA) begin
+    if (riscv::IS_XLEN64) begin : gen_amo_64b_data
+      assign amo_data_a = {amo_req_i.operand_b[0 +: 32], amo_req_i.operand_b[0 +: 32]};
+      assign amo_data_b = amo_req_i.operand_b;
+    end else begin : gen_amo_32b_data
+      assign amo_data_a = amo_req_i.operand_b[0 +: 32];
     end
   end
 
-  if (CVA6Cfg.RVA) begin
-      // note: openpiton returns a full cacheline!
-      if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
-        if (CVA6Cfg.AxiDataWidth > 64) begin
-          assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64];
+  always_comb begin
+    if (CVA6Cfg.RVA) begin
+      if (riscv::IS_XLEN64) begin
+        if (amo_req_i.size == 2'b10) begin
+          amo_data = amo_data_a;
         end else begin
-          assign amo_rtrn_mux = mem_rtrn_i.data[0 +: 64];
+          amo_data = amo_data_b;
         end
-      end else begin : gen_piton_rtrn_mux
-        assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[DCACHE_OFFSET_WIDTH-1:3]*64 +: 64];
+      end else begin
+        amo_data = amo_data_a;
       end
+      if (ariane_pkg::DATA_USER_EN) begin
+        amo_user = amo_data;
+      end else begin
+        amo_user = '0;
+      end
+    end
+  end
 
-      // always sign extend 32bit values
-      assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} :
-                                                           amo_rtrn_mux ;
-
-      assign amo_req_d = amo_req_i.req;
+  if (CVA6Cfg.RVA) begin
+    // note: openpiton returns a full cacheline!
+    if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
+      if (CVA6Cfg.AxiDataWidth > 64) begin
+        assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(
+            CVA6Cfg.AxiDataWidth/8
+        )-1:3]*64+:64];
+      end else begin
+        assign amo_rtrn_mux = mem_rtrn_i.data[0+:64];
+      end
+    end else begin : gen_piton_rtrn_mux
+      assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[DCACHE_OFFSET_WIDTH-1:3]*64+:64];
+    end
 
+    // always sign extend 32bit values
+    assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} :
+                                                       amo_rtrn_mux ;
+    assign amo_req_d = amo_req_i.req;
   end
 
   // outgoing memory requests (AMOs are always uncached)
-  assign mem_data_o.tid    = (CVA6Cfg.RVA && amo_sel) ? AmoTxId             : miss_id_i[miss_port_idx];
-  assign mem_data_o.nc     = (CVA6Cfg.RVA && amo_sel) ? 1'b1                : miss_nc_i[miss_port_idx];
-  assign mem_data_o.way    = (CVA6Cfg.RVA && amo_sel) ? '0                  : repl_way;
-  assign mem_data_o.data   = (CVA6Cfg.RVA && amo_sel) ? amo_data            : miss_wdata_i[miss_port_idx];
-  assign mem_data_o.user   = (CVA6Cfg.RVA && amo_sel) ? amo_user            : miss_wuser_i[miss_port_idx];
-  assign mem_data_o.size   = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.size      : miss_size_i [miss_port_idx];
-  assign mem_data_o.amo_op = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.amo_op    : AMO_NONE;
+  assign mem_data_o.tid    = (CVA6Cfg.RVA && amo_sel) ? AmoTxId                : miss_id_i[miss_port_idx];
+  assign mem_data_o.nc     = (CVA6Cfg.RVA && amo_sel) ? 1'b1                   : miss_nc_i[miss_port_idx];
+  assign mem_data_o.way    = (CVA6Cfg.RVA && amo_sel) ? '0                     : repl_way;
+  assign mem_data_o.data   = (CVA6Cfg.RVA && amo_sel) ? amo_data               : miss_wdata_i[miss_port_idx];
+  assign mem_data_o.user   = (CVA6Cfg.RVA && amo_sel) ? amo_user               : miss_wuser_i[miss_port_idx];
+  assign mem_data_o.size   = (CVA6Cfg.RVA && amo_sel) ? {1'b0, amo_req_i.size} : miss_size_i [miss_port_idx];
+  assign mem_data_o.amo_op = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.amo_op       : AMO_NONE;
 
   assign tmp_paddr         = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.operand_a[riscv::PLEN-1:0] : miss_paddr_i[miss_port_idx];
   assign mem_data_o.paddr  = paddrSizeAlign(tmp_paddr, mem_data_o.size);

core/cache_subsystem/wt_dcache_wbuffer.sv

@@ -167,7 +167,7 @@ module wt_dcache_wbuffer
 
   for (genvar k = 0; k < DCACHE_MAX_TX; k++) begin : gen_tx_vld
     assign tx_vld_o[k]   = tx_stat_q[k].vld;
-    assign tx_paddr_o[k] = wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES;
+    assign tx_paddr_o[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES};
   end
 
   ///////////////////////////////////////////////////////
@@ -201,8 +201,11 @@ module wt_dcache_wbuffer
   // note: openpiton can only handle aligned offsets + size, and hence
   // we have to split unaligned data into multiple transfers (see toSize64)
   // e.g. if we have the following valid bytes: 0011_1001 -> TX0: 0000_0001, TX1: 0000_1000, TX2: 0011_0000
-
-  assign miss_size_o = riscv::IS_XLEN64 ? toSize64(bdirty[dirty_ptr]) : toSize32(bdirty[dirty_ptr]);
+  if(riscv::IS_XLEN64) begin : gen_size_64b
+    assign miss_size_o = {1'b0, toSize64(bdirty[dirty_ptr])};
+  end else begin : gen_size_32b
+    assign miss_size_o = {1'b0, toSize32(bdirty[dirty_ptr])};
+  end
 
   // replicate transfers shorter than a dword
   assign miss_wdata_o = riscv::IS_XLEN64 ? repData64(
@@ -308,7 +311,7 @@ module wt_dcache_wbuffer
 
   // trigger TAG readout in cache
   assign rd_tag_only_o = 1'b1;
-  assign rd_paddr      = wbuffer_check_mux.wtag << riscv::XLEN_ALIGN_BYTES;
+  assign rd_paddr      = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_check_mux.wtag << riscv::XLEN_ALIGN_BYTES};
   assign rd_req_o      = |tocheck;
   assign rd_tag_o      = rd_tag_q;  //delay by one cycle
   assign rd_idx_o      = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH];
@@ -320,7 +323,7 @@ module wt_dcache_wbuffer
   // if we wrote into a word while it was in-flight, we cannot write the dirty bytes to the cache
   // when the TX returns
   assign wr_data_be_o  = tx_stat_q[rtrn_id].be & (~wbuffer_q[rtrn_ptr].dirty);
-  assign wr_paddr      = wbuffer_q[rtrn_ptr].wtag << riscv::XLEN_ALIGN_BYTES;
+  assign wr_paddr      = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[rtrn_ptr].wtag << riscv::XLEN_ALIGN_BYTES};
   assign wr_idx_o      = wr_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH];
   assign wr_off_o      = wr_paddr[DCACHE_OFFSET_WIDTH-1:0];
   assign wr_data_o     = wbuffer_q[rtrn_ptr].data;
@@ -338,7 +341,7 @@ module wt_dcache_wbuffer
 
   for (genvar k = 0; k < DCACHE_WBUF_DEPTH; k++) begin : gen_flags
     // only for debug, will be pruned
-    assign debug_paddr[k] = wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES;
+    assign debug_paddr[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES};
 
     // dirty bytes that are ready for transmission.
     // note that we cannot retransmit a word that is already in-flight

core/cvxif_fu.sv

@@ -33,10 +33,18 @@ module cvxif_fu
     output cvxif_pkg::cvxif_req_t                      cvxif_req_o,
     input  cvxif_pkg::cvxif_resp_t                     cvxif_resp_i
 );
+  localparam X_NUM_RS     = ariane_pkg::NR_RGPR_PORTS;
 
   logic illegal_n, illegal_q;
   logic [TRANS_ID_BITS-1:0] illegal_id_n, illegal_id_q;
   logic [31:0] illegal_instr_n, illegal_instr_q;
+  logic [X_NUM_RS-1:0] rs_valid;
+
+  if (cvxif_pkg::X_NUM_RS == 3) begin : gen_third_operand
+    assign rs_valid = 3'b111;
+  end else begin : gen_no_third_operand
+    assign rs_valid = 2'b11;
+  end
 
   always_comb begin
     cvxif_req_o = '0;
@@ -52,7 +60,7 @@ module cvxif_fu
       if (cvxif_pkg::X_NUM_RS == 3) begin
         cvxif_req_o.x_issue_req.rs[2] = fu_data_i.imm;
       end
-      cvxif_req_o.x_issue_req.rs_valid   = cvxif_pkg::X_NUM_RS == 3 ? 3'b111 : 2'b11;
+      cvxif_req_o.x_issue_req.rs_valid   = rs_valid;
       cvxif_req_o.x_commit_valid         = x_valid_i;
       cvxif_req_o.x_commit.id            = fu_data_i.trans_id;
       cvxif_req_o.x_commit.x_commit_kill = 1'b0;

core/include/wt_cache_pkg.sv

@@ -115,7 +115,7 @@ package wt_cache_pkg;
     logic                                      vld;  // invalidate only affected way
     logic                                      all;  // invalidate all ways
     logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx;  // physical address to invalidate
-    logic [L15_WAY_WIDTH-1:0]                  way;  // way to invalidate
+    logic [L1I_WAY_WIDTH-1:0]                  way;  // way to invalidate
   } icache_inval_t;
 
   typedef struct packed {
@@ -265,8 +265,8 @@ package wt_cache_pkg;
     return cnt;
   endfunction : popcnt64
 
-  function automatic logic [7:0] to_byte_enable8(input logic [2:0] offset, input logic [1:0] size);
-    logic [7:0] be;
+  function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8(input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
+    logic [(riscv::XLEN/8)-1:0] be;
     be = '0;
     unique case (size)
       2'b00:   be[offset] = '1;  // byte
@@ -277,7 +277,7 @@ package wt_cache_pkg;
     return be;
   endfunction : to_byte_enable8
 
-  function automatic logic [3:0] to_byte_enable4(input logic [1:0] offset, input logic [1:0] size);
+  function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4(input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
     logic [3:0] be;
     be = '0;
     unique case (size)
@@ -289,9 +289,9 @@ package wt_cache_pkg;
   endfunction : to_byte_enable4
 
   // openpiton requires the data to be replicated in case of smaller sizes than dwords
-  function automatic logic [63:0] repData64(input logic [63:0] data, input logic [2:0] offset,
+  function automatic riscv::xlen_t repData64(input riscv::xlen_t data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
                                             input logic [1:0] size);
-    logic [63:0] out;
+    riscv::xlen_t out;
     unique case (size)
       2'b00:   for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8];  // byte
       2'b01:   for (int k = 0; k < 4; k++) out[k*16+:16] = data[offset*8+:16];  // hword
@@ -301,9 +301,9 @@ package wt_cache_pkg;
     return out;
   endfunction : repData64
 
-  function automatic logic [31:0] repData32(input logic [31:0] data, input logic [1:0] offset,
+  function automatic riscv::xlen_t repData32(input riscv::xlen_t data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
                                             input logic [1:0] size);
-    logic [31:0] out;
+    riscv::xlen_t out;
     unique case (size)
       2'b00:   for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8];  // byte
       2'b01:   for (int k = 0; k < 2; k++) out[k*16+:16] = data[offset*8+:16];  // hword