Updating MTVEC and STVEC description

openhwgroup · Jul 31, 2023 · 3deb46f · 3deb46f
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diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.md b/docs/01_cva6_user/ip-xact/cva6_csr.md
@@ -75,8 +75,8 @@ The ``sie`` is the register containing supervisor interrupt enable bits.
 The ``stvec`` register holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
 | BIT |  NAME       | displayName        | RIGHT  | Description                                                          |
 | --- | ----------- | ------------       | ------ | -------------------------------------------------------------------- |
-| 31:2 | BASE |  | read-write,WARL  | The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4\-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field\.|
-| 1:0 | MODE |  | read-write,WARL  | When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\.``Legal Values :``0\. // ``Enumerated Values``( "Direct" :0 ) ( "Vectored" :1 ) ( "Reserved_2" :2 ) ( "Reserved_3" :3 ) |
+| 31:2 | BASE |  | read-write,WARL  | The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\.|
+| 1:0 | MODE |  | read-write,WARL  | When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\.``Legal Values :``0,1\. // ``Enumerated Values``( "Direct" :0 ) ( "Vectored" :1 ) ( "Reserved_2" :2 ) ( "Reserved_3" :3 ) |
 
 ## Supervisor Counter Enable Register 
 ### *AddressOffset*: 'h106 
@@ -257,8 +257,8 @@ This register contains machine interrupt enable bits.
 This register holds trap vector configuration, consisting of a vector base address and a vector mode.
 | BIT |  NAME       | displayName        | RIGHT  | Description                                                          |
 | --- | ----------- | ------------       | ------ | -------------------------------------------------------------------- |
-| 31:2 | BASE |  | read-write,WARL  | Holds the vector base address\. The value in the BASE field must always be aligned on a 4\-byte boundary\.|
-| 1:0 | MODE |  | read-write,WARL  | Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0\. // ``Enumerated Values``( "Direct" :0 ) ( "Vectored" :1 ) ( "Reserved_2" :2 ) ( "Reserved_3" :3 ) |
+| 31:2 | BASE |  | read-write,WARL  | The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\.|
+| 1:0 | MODE |  | read-write,WARL  | Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0,1\. // ``Enumerated Values``( "Direct" :0 ) ( "Vectored" :1 ) ( "Reserved_2" :2 ) ( "Reserved_3" :3 ) |
 
 ## Machine Counter Enable Register 
 ### *AddressOffset*: 'h306 

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.rst b/docs/01_cva6_user/ip-xact/cva6_csr.rst
@@ -258,12 +258,12 @@ The ``stvec`` register holds trap vector configuration, consisting of a vector b
      - BASE
      - 
      - read-write,WARL
-     - The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4\-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field\.
+     - The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\.
    * - 1:0
      - MODE
      - 
      - read-write,WARL
-     - When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\.``Legal Values :``0\.  ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n'
+     - When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\.``Legal Values :``0,1\.  ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n'
 
 Supervisor Counter Enable Register 
 --------------------------
@@ -861,12 +861,12 @@ This register holds trap vector configuration, consisting of a vector base addre
      - BASE
      - 
      - read-write,WARL
-     - Holds the vector base address\. The value in the BASE field must always be aligned on a 4\-byte boundary\.
+     - The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\.
    * - 1:0
      - MODE
      - 
      - read-write,WARL
-     - Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0\.  ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n'
+     - Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0,1\.  ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n'
 
 Machine Counter Enable Register 
 --------------------------

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.xml b/docs/01_cva6_user/ip-xact/cva6_csr.xml
@@ -643,7 +643,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
                                         <ipxact:access>read-write</ipxact:access>
                                         <ipxact:field>
                                                 <ipxact:name>BASE</ipxact:name>
-                                                <ipxact:description>The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.</ipxact:description>
+                                                <ipxact:description>The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.</ipxact:description>
                                                 <ipxact:bitOffset>2</ipxact:bitOffset>
                                                 <ipxact:resets>
                                                         <ipxact:reset>
@@ -659,7 +659,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
                                         </ipxact:field>
                                         <ipxact:field>
                                                 <ipxact:name>MODE</ipxact:name>
-                                                <ipxact:description>When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0.</ipxact:description>
+                                                <ipxact:description>When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0,1.</ipxact:description>
                                                 <ipxact:bitOffset>0</ipxact:bitOffset>
                                                 <ipxact:resets>
                                                         <ipxact:reset>
@@ -1923,7 +1923,7 @@ with the index of the bit position equal to the value returned in the ``mcause``
                                         <ipxact:access>read-write</ipxact:access>
                                         <ipxact:field>
                                                 <ipxact:name>BASE</ipxact:name>
-                                                <ipxact:description>Holds the vector base address. The value in the BASE field must always be aligned on a 4-byte boundary.</ipxact:description>
+                                                <ipxact:description>The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.</ipxact:description>
                                                 <ipxact:bitOffset>2</ipxact:bitOffset>
                                                 <ipxact:resets>
                                                         <ipxact:reset>
@@ -1939,7 +1939,7 @@ with the index of the bit position equal to the value returned in the ``mcause``
                                         </ipxact:field>
                                         <ipxact:field>
                                                 <ipxact:name>MODE</ipxact:name>
-                                                <ipxact:description>Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0.</ipxact:description>
+                                                <ipxact:description>Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1.</ipxact:description>
                                                 <ipxact:bitOffset>0</ipxact:bitOffset>
                                                 <ipxact:resets>
                                                         <ipxact:reset>

diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.yaml b/docs/01_cva6_user/ip-xact/cva6_csr.yaml
@@ -478,7 +478,7 @@ component:
           access: read-write
           field:
           - name: BASE
-            description: 'The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.'
+            description: 'The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.'
             bitOffset: '2'
             resets:
               reset:
@@ -489,7 +489,7 @@ component:
             vendorExtensions:
               RISCV_behavior: WARL
           - name: MODE
-            description: When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0.
+            description: When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0,1.
             bitOffset: '0'
             resets:
               reset:
@@ -1380,7 +1380,7 @@ component:
           access: read-write
           field:
           - name: BASE
-            description: Holds the vector base address. The value in the BASE field must always be aligned on a 4-byte boundary.
+            description: 'The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.'
             bitOffset: '2'
             resets:
               reset:
@@ -1391,7 +1391,7 @@ component:
             vendorExtensions:
               RISCV_behavior: WARL
           - name: MODE
-            description: Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0.
+            description: Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1.
             bitOffset: '0'
             resets:
               reset: