Revert "Multicommits to shorten smoke-tests duration, to declare VLEN…

… as para…"

This reverts commit 0877e8e.

.gitlab-ci.yml

@@ -135,23 +135,7 @@ build_tools:
   - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
   - if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
 
-smoke-tests-cv32a65x:
-  extends:
-    - .fe_smoke_test
-  variables:
-    DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
-    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
-    DASHBOARD_SORT_INDEX: 0
-    DASHBOARD_JOB_CATEGORY: "Basic"
-    SPIKE_TANDEM: 1
-    COLLECT_SIMU_LOGS: 1
-    DV_SIMULATORS: "vcs-uvm"
-  script:
-    - bash verif/regress/smoke-tests-cv32a65x.sh
-    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
-    - !reference [.simu_after_script]
-
-smoke-tests-cv32a6_imac_sv32:
+smoke:
   extends:
     - .fe_smoke_test
   variables:
@@ -166,34 +150,14 @@ smoke-tests-cv32a6_imac_sv32:
       - DV_SIMULATORS:
         - "vcs-testharness"
         - "questa-testharness"
+        - "vcs-uvm"
   script:
     - source $QUESTA_BASHRC
-    - bash verif/regress/smoke-tests-cv32a6_imac_sv32.sh
+    - bash verif/regress/smoke-tests.sh
     - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
     - !reference [.simu_after_script]
 
-smoke-tests-cv64a6_imafdc_sv39:
-  extends:
-    - .fe_smoke_test
-  variables:
-    DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
-    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
-    DASHBOARD_SORT_INDEX: 0
-    DASHBOARD_JOB_CATEGORY: "Basic"
-    SPIKE_TANDEM: 1
-    COLLECT_SIMU_LOGS: 1
-  parallel:
-    matrix:
-      - DV_SIMULATORS:
-        - "vcs-testharness"
-        - "questa-testharness"
-  script:
-    - source $QUESTA_BASHRC
-    - bash verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh
-    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
-    - !reference [.simu_after_script]
-
-smoke-gen:
+gen_smoke:
   extends:
     - .fe_smoke_test
   variables:
@@ -217,23 +181,24 @@ smoke-bench:
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Performance"
     SPIKE_TANDEM: 1
-    BENCH: "dhrystone"
+  parallel:
+    matrix:
+      - BENCH: "dhrystone"
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"]
   script:
     - bash verif/regress/"$BENCH"_smoke.sh --no-print
     - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_cv32a65x verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
 
-smoke-hwconfig:
+hwconfig:
   extends:
     - .fe_smoke_test
   variables:
     DASHBOARD_JOB_TITLE: "HW config $DV_SIMULATORS $DV_HWCONFIG_OPTS"
     DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations"
     DASHBOARD_SORT_INDEX: 1
     DASHBOARD_JOB_CATEGORY: "Basic"
-    DV_SIMULATORS: "vcs-uvm"
-    SPIKE_TANDEM: 1
-    DV_TARGET: "hwconfig"
-    DV_HWCONFIG_OPTS: "cv32a65x"
+    DV_SIMULATORS: "veri-testharness,spike"
+    DV_HWCONFIG_OPTS: "cv32a6_imac_sv32"
   script:
     - source verif/regress/hwconfig_tests.sh
     - python3 .gitlab-ci/scripts/report_pass.py
@@ -361,16 +326,16 @@ benchmarks:
     matrix:
       - BENCH: "dhrystone"
         ISSUE: "single"
-        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"]
       - BENCH: "dhrystone"
         ISSUE: "dual"
-        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"]
       - BENCH: "coremark"
         ISSUE: "single"
-        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=0 IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"]
       - BENCH: "coremark"
         ISSUE: "dual"
-        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=32768 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8"]
   script:
     - bash verif/regress/"$BENCH".sh
     - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log

.gitlab-ci/scripts/report_benchmark.py

@@ -19,11 +19,11 @@
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    "dhrystone_dual": 20199,
-    "dhrystone_single": 25019,
-    "coremark_dual": 1017451,
-    "coremark_single": 1308656,
-    "dhrystone_cv32a65x": 32566,
+    "dhrystone_dual": 21530,
+    "dhrystone_single": 26392,
+    "coremark_dual": 530099,
+    "coremark_single": 673184,
+    "dhrystone_cv32a65x": 33736,
 }
 
 for arg in sys.argv[1:]:
@@ -32,7 +32,7 @@
             iterations = 50
         else:
             if "--coremark" in arg:
-                iterations = 4
+                iterations = 2
         mode = arg.replace("-", "")
     else:
         path = arg

README.md

@@ -97,7 +97,7 @@ cd ./verif/sim
 
 python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \
 --c_tests ../tests/custom/hello_world/hello_world.c \
---linker=../../config/gen_from_riscv_config/linker/link.ld \
+--linker=../tests/custom/common/test.ld \
 --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \
 -nostartfiles -g ../tests/custom/common/syscalls.c \
 ../tests/custom/common/crt.S -lgcc \

core/frontend/instr_queue.sv

@@ -369,7 +369,7 @@ module instr_queue
             end
             fetch_entry_o[NID].instruction = instr_data_out[i].instr;
             fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
-            fetch_entry_o[NID].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
+            fetch_entry_o[NID].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
             fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf;
             // Cannot output two CF the same cycle.
             pop_instr[i] = fetch_entry_fire[NID];

core/include/build_config_pkg.sv

@@ -32,7 +32,7 @@ package build_config_pkg;
     config_pkg::cva6_cfg_t cfg;
 
     cfg.XLEN = CVA6Cfg.XLEN;
-    cfg.VLEN = CVA6Cfg.VLEN;
+    cfg.VLEN = (CVA6Cfg.XLEN == 32) ? 32 : 64;
     cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56;
     cfg.GPLEN = (CVA6Cfg.XLEN == 32) ? 34 : 41;
     cfg.IS_XLEN32 = IS_XLEN32;

core/include/config_pkg.sv

@@ -48,8 +48,6 @@ package config_pkg;
   typedef struct packed {
     // General Purpose Register Size (in bits)
     int unsigned                 XLEN;
-    // Virtual address Size (in bits)
-    int unsigned                 VLEN;
     // Atomic RISC-V extension
     bit                          RVA;
     // Bit manipulation RISC-V extension

core/include/cv32a65x_config_pkg.sv

@@ -20,7 +20,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(32),
       FpgaEn: bit'(0),
       TechnoCut: bit'(1),
       SuperscalarEn: bit'(1),

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(32),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(32),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(32),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(32),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -81,7 +81,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdch_sv39_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -74,7 +74,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(CVA6ConfigFpgaEn),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/cv64a6_mmu_config_pkg.sv

@@ -27,7 +27,6 @@ package cva6_config_pkg;
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
-      VLEN: unsigned'(64),
       FpgaEn: bit'(0),
       TechnoCut: bit'(0),
       SuperscalarEn: bit'(0),

core/include/riscv_pkg.sv

@@ -23,6 +23,7 @@ package riscv;
   // FIXME stop using them from CoreV-Verif and HPDCache
   // Then remove them from this package
   localparam XLEN = cva6_config_pkg::CVA6ConfigXlen;
+  localparam VLEN = (XLEN == 32) ? 32 : 64;
   localparam PLEN = (XLEN == 32) ? 34 : 56;
 
   // --------------------

core/instr_realign.sv

@@ -127,7 +127,7 @@ module instr_realign
       instr_o[2]          = '0;
       addr_o[2]           = '0;
       instr_o[3]          = {16'b0, data_i[63:48]};
-      addr_o[3]           = {address_i[CVA6Cfg.VLEN-1:3], 3'b110};
+      addr_o[3]           = {address_i[riscv::VLEN-1:3], 3'b110};
 
       case (address_i[2:1])
         2'b00: begin
@@ -153,11 +153,11 @@ module instr_realign
             addr_o[0]  = unaligned_address_q;
 
             instr_o[1] = data_i[47:16];
-            addr_o[1]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b010};
+            addr_o[1]  = {address_i[riscv::VLEN-1:3], 3'b010};
 
             if (instr_is_compressed[1]) begin
               instr_o[2] = data_i[63:32];
-              addr_o[2]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b100};
+              addr_o[2]  = {address_i[riscv::VLEN-1:3], 3'b100};
               valid_o[2] = valid_i;
 
               if (instr_is_compressed[2]) begin
@@ -189,7 +189,7 @@ module instr_realign
 
             if (instr_is_compressed[0]) begin
               instr_o[1] = data_i[47:16];
-              addr_o[1]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b010};
+              addr_o[1]  = {address_i[riscv::VLEN-1:3], 3'b010};
 
               //     64  48  32  16  0
               //     | 3 | 2 | 1 | 0 | <- instruction slot
@@ -200,7 +200,7 @@ module instr_realign
               // | * | C | C | C | C | -> aligned
               if (instr_is_compressed[1]) begin
                 instr_o[2] = data_i[63:32];
-                addr_o[2]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b100};
+                addr_o[2]  = {address_i[riscv::VLEN-1:3], 3'b100};
                 valid_o[2] = valid_i;
 
                 if (instr_is_compressed[2]) begin
@@ -231,7 +231,7 @@ module instr_realign
               // | * | C | C |   I   |
               // | * |   I   |   I   |
               instr_o[1] = data_i[63:32];
-              addr_o[1]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b100};
+              addr_o[1]  = {address_i[riscv::VLEN-1:3], 3'b100};
 
               instr_o[2] = instr_o[3];
               addr_o[2]  = addr_o[3];
@@ -262,15 +262,15 @@ module instr_realign
           //   000 110 100 010 <- unaligned address
 
           instr_o[0] = data_i[31:0];
-          addr_o[0]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b010};
+          addr_o[0]  = {address_i[riscv::VLEN-1:3], 3'b010};
           valid_o[0] = valid_i;
 
           instr_o[2] = data_i[63:32];
-          addr_o[2]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b110};
+          addr_o[2]  = {address_i[riscv::VLEN-1:3], 3'b110};
 
           if (instr_is_compressed[0]) begin
             instr_o[1] = data_i[47:16];
-            addr_o[1]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b100};
+            addr_o[1]  = {address_i[riscv::VLEN-1:3], 3'b100};
             valid_o[1] = valid_i;
 
             if (instr_is_compressed[1]) begin
@@ -304,11 +304,11 @@ module instr_realign
           //      1000 110 100 <- unaligned address
 
           instr_o[0] = data_i[31:0];
-          addr_o[0]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b100};
+          addr_o[0]  = {address_i[riscv::VLEN-1:3], 3'b100};
           valid_o[0] = valid_i;
 
           instr_o[1] = data_i[47:16];
-          addr_o[1]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b110};
+          addr_o[1]  = {address_i[riscv::VLEN-1:3], 3'b110};
 
           if (instr_is_compressed[0]) begin
             if (instr_is_compressed[1]) begin
@@ -330,7 +330,7 @@ module instr_realign
           //          1000 110 <- unaligned address
 
           instr_o[0] = data_i[31:0];
-          addr_o[0]  = {address_i[CVA6Cfg.VLEN-1:3], 3'b110};
+          addr_o[0]  = {address_i[riscv::VLEN-1:3], 3'b110};
 
           if (instr_is_compressed[0]) begin
             valid_o[0] = valid_i;