Performance tb (#2562)

For reminder, the option --issrun_opts="+tb_performance_mode" allows to disable UVM features like assertion and log generation to reduce simulation time.
openhwgroup · Oct 23, 2024 · 20b64e8 · 20b64e8
1 parent 21dc824
commit 20b64e8
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Showing 5 changed files with 29 additions and 5 deletions.
diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh
@@ -38,6 +38,8 @@ if ! [ -n "$UVM_VERBOSITY" ]; then
     export UVM_VERBOSITY=UVM_NONE
 fi
 
+export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
 make clean
 make -C verif/sim clean_all
 
@@ -92,5 +94,4 @@ python3 cva6.py \
         --c_tests "$src0" \
         --gcc_opts "${srcA[*]} ${cflags[*]}" \
         --iss_timeout=2000 \
-        --issrun_opts="+tb_performance_mode" \
         $DV_OPTS
diff --git a/verif/regress/dhrystone.sh b/verif/regress/dhrystone.sh
@@ -29,6 +29,12 @@ if ! [ -n "$DV_HWCONFIG_OPTS" ]; then
   DV_HWCONFIG_OPTS="cv32a65x"
 fi
 
+if ! [ -n "$UVM_VERBOSITY" ]; then
+    export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
 make clean
 make -C verif/sim clean_all
 
@@ -63,5 +69,4 @@ python3 cva6.py \
         --iss="$DV_SIMULATORS" \
         --iss_yaml=cva6.yaml \
         --c_tests "$src0" \
-        --issrun_opts="+tb_performance_mode" \
         --gcc_opts "${srcA[*]} ${cflags[*]}"
diff --git a/verif/regress/dv-riscv-arch-test.sh b/verif/regress/dv-riscv-arch-test.sh
@@ -35,5 +35,11 @@ else
   TESTLIST=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml
 fi
 
+if ! [ -n "$UVM_VERBOSITY" ]; then
+    export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
 cd verif/sim
-python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
+python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
diff --git a/verif/regress/dv-riscv-compliance.sh b/verif/regress/dv-riscv-compliance.sh
@@ -28,6 +28,12 @@ if ! [ -n "$DV_SIMULATORS" ]; then
   DV_SIMULATORS=veri-testharness,spike
 fi
 
+if ! [ -n "$UVM_VERBOSITY" ]; then
+    export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
 cd verif/sim
-python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
 cd -
diff --git a/verif/regress/dv-riscv-tests.sh b/verif/regress/dv-riscv-tests.sh
@@ -33,9 +33,15 @@ if ! [ -n "$DV_TESTLISTS" ]; then
                 ../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
 fi
 
+if ! [ -n "$UVM_VERBOSITY" ]; then
+    export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
 cd verif/sim
 for TESTLIST in $DV_TESTLISTS
 do
-  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --issrun_opts="+tb_performance_mode" $DV_OPTS
+  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
 done
 cd -