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Merge pull request #834 from Silabs-ArjanB/ArjanB_debuga23
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Updated RISC-V Debug specification to version 1.0-STABLE, fb702526127…
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@silabs-oysteink
silabs-oysteink authored Apr 19, 2023
2 parents 3372cb3 + c91c4b2 commit f17028f
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81 changes: 14 additions & 67 deletions docs/user_manual/source/control_status_registers.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -90,12 +90,8 @@ instruction exception.
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7A2 | ``tdata2`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Data Register 2 |
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7A3 | ``tdata3`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Data Register 3 |
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7A4 | ``tinfo`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Info |
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7A5 | ``tcontrol`` | MRW | ``DBG_NUM_TRIGGERS`` > 0 | Trigger Control |
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7B0 | ``dcsr`` | DRW | ``DEBUG`` = 1 | Debug Control and Status |
+---------------+-------------------+-----------+--------------------------+---------------------------------------------------------+
| 0x7B1 | ``dpc`` | DRW | ``DEBUG`` = 1 | Debug PC |
Expand Down Expand Up @@ -1556,20 +1552,21 @@ Reset Value: Not applicable
+-------+-------------+----------------------------------------------------------------+
| 27 | WARL (0x1) | **DMODE**. Only debug mode can write ``tdata`` registers. |
+-------+-------------+----------------------------------------------------------------+
| 26:25 | WARL (0x0) | Hardwired to 0. |
| 26 | WARL (0x0) | **UNCERTAIN**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 25 | | **HIT1**. Forms 2-bit WARL (0x0, 0x1) bitfield with **HIT0**. |
+-------+-------------+----------------------------------------------------------------+
| 24 | WARL (0x0) | **VS**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 23 | WARL (0x0) | **VU**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 22 | WARL (0x0) | **HIT**. Hardwired to 0. |
| 22 | | **HIT0**. Forms 2-bit WARL (0x0, 0x1) bitfield with **HIT1**. |
+-------+-------------+----------------------------------------------------------------+
| 21 | WARL (0x0) | **SELECT**. Only address matching is supported. |
+-------+-------------+----------------------------------------------------------------+
| 20 | WARL (0x0) | **TIMING**. Break before the instruction at the specified |
| | | address. |
| 20:19 | WARL (0x0) | Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 19:16 | WARL (0x0) | **SIZE**. Match accesses of any size. |
| 18:16 | WARL (0x0) | **SIZE**. Match accesses of any size. |
+-------+-------------+----------------------------------------------------------------+
| 15:12 | WARL (0x1) | **ACTION**. Enter debug mode on match. |
+-------+-------------+----------------------------------------------------------------+
Expand All @@ -1580,7 +1577,7 @@ Reset Value: Not applicable
+-------+-------------+----------------------------------------------------------------+
| 6 | WARL | **M**. Match in machine mode. |
+-------+-------------+----------------------------------------------------------------+
| 5 | WARL (0x0) | Hardwired to 0. |
| 5 | WARL (0x0) | **UNCERTAINEN**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 4 | WARL (0x0) | **S**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
Expand All @@ -1593,6 +1590,9 @@ Reset Value: Not applicable
| 0 | WARL | **LOAD**. Enable matching on load address. |
+-------+-------------+----------------------------------------------------------------+

.. note::
The ``hit1`` (MSB) and ``hit0`` (LSB) bitfields form a 2-bit bitfield together that has WARL (0x0, 0x1) behavior.

.. _csr-tdata1_disabled:

Trigger Data 1 (``tdata1``) - ``disabled`` view
Expand Down Expand Up @@ -1769,38 +1769,14 @@ Detailed:
.. note::
Accessible in Debug Mode or M-Mode, depending on ``tdata1.DMODE``.

.. _csr-tdata3:

Trigger Data Register 3 (``tdata3``)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

CSR Address: 0x7A3

Reset Value: 0x0000_0000

Detailed:

.. table::
:widths: 10 20 70
:class: no-scrollbar-table

+-------+------------+------------------------------------------------------------------+
| Bit# | R/W | Description |
+=======+============+==================================================================+
| 31:0 | WARL (0x0) | Hardwired to 0. |
+-------+------------+------------------------------------------------------------------+

Accessible in Debug Mode or M-Mode.
|corev| does not support the features requiring this register. CSR is hardwired to 0.

.. _csr-tinfo:

Trigger Info (``tinfo``)
~~~~~~~~~~~~~~~~~~~~~~~~

CSR Address: 0x7A4

Reset Value: 0x0000_8064
Reset Value: 0x0100_8064

Detailed:

Expand All @@ -1811,7 +1787,9 @@ Detailed:
+-------+------------+------------------------------------------------------------------+
| Bit# | R/W | Description |
+=======+============+==================================================================+
| 31:16 | WARL (0x0) | Hardwired to 0. |
| 31:24 | R (0x1) | **VERSION**. Sdtrig version 1.0. |
+-------+------------+------------------------------------------------------------------+
| 23:16 | WARL (0x0) | Hardwired to 0. |
+-------+------------+------------------------------------------------------------------+
| 15:0 | R (0x8064) | **INFO**. Types 0x2, 0x5, 0x6 and 0xF are supported. |
+-------+------------+------------------------------------------------------------------+
Expand All @@ -1823,37 +1801,6 @@ does not exist, this field contains 1.

Accessible in Debug Mode or M-Mode.

.. _csr-tcontrol:

Trigger Control (``tcontrol``)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

CSR Address: 0x7A5

Reset Value: 0x0000_0000

Detailed:

.. table::
:widths: 10 20 70
:class: no-scrollbar-table

+-------+-------------+------------------------------------------------------------------+
| Bit# | R/W | Description |
+=======+=============+==================================================================+
| 31:8 | WARL (0x0) | Hardwired to 0. |
+-------+-------------+------------------------------------------------------------------+
| 7 | WARL (0x0) | **MPTE**. Hardwired to 0. |
+-------+-------------+------------------------------------------------------------------+
| 6:4 | WARL (0x0) | Hardwired to 0. |
+-------+-------------+------------------------------------------------------------------+
| 3 | WARL (0x0) | **MTE**. Hardwired to 0. |
+-------+-------------+------------------------------------------------------------------+
| 2:0 | WARL (0x0) | Hardwired to 0. |
+-------+-------------+------------------------------------------------------------------+

|corev| does not support the features requiring this register. CSR is hardwired to 0.

.. _csr-dcsr:

Debug Control and Status (``dcsr``)
Expand Down
4 changes: 2 additions & 2 deletions docs/user_manual/source/intro.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,8 @@ It follows these specifications:
.. [RISC-V-RV32E] RISC-V Instruction Set Manual, Volume I: User-Level ISA, RV32E Base Integer Instruction Set, Document version 20191214-draft (January 31, 2023),
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/riscv-spec.pdf
.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, 246028cd719426597269b3d717c866802c58bde7,
https://github.com/riscv/riscv-debug-spec/blob/05252da1575610e9605d882145da3f4e7f4f3cb1/riscv-debug-stable.pdf
.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, fb702526127d0c8a4b343fc017e2c93137177df0, April 14 2023,
https://github.com/riscv/riscv-debug-spec/blob/f4381fed042927d9d1fba774898ae2484e5cdc71/riscv-debug-stable.pdf
.. [RISC-V-CLIC] Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions, version 0.9-draft, 4/11/2023,
https://github.com/riscv/riscv-fast-interrupt/blob/ec831f3db6bd896336a9008263b4263177eb608c/clic.pdf
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