update 'csr_access_test'

Signed-off-by: Robin Pedersen <[email protected]>
openhwgroup · Sep 7, 2023 · d5ef816 · d5ef816
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diff --git a/tests/programs/custom/cv32e40x_csr_access_test/README.md b/tests/programs/custom/cv32e40x_csr_access_test/README.md
@@ -5,20 +5,17 @@ Generated from "riscv-dv"'s `scripts/gen_csr_test.py`, via core-v-verif's
 
 From top-level:
 ```
-python3 ./bin/gen_csr_access_test.py  \
+./bin/gen_csr_access_test.py  \
   --core=cv32e40x     \
   --clint_enable      \
   --i_base_enable     \
   --m_ext_enable      \
-  --umode_enable      \
   --zc_enable         \
-  --mhpmcounter_num 0 \
+  --mhpmcounter_num 1 \
   --num_triggers    0 \
   --pmp_num_regions 0 \
   --output=./cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/ \
   --m4
 ```
 The above options were the most applicable at the time of writing and are subject to change.
 Note that excluded options and parameters need targeted separate testing.
-
-[comment]: # (TODO:silabs-robin Regen with "--xsecure_enable" etc after iss bugfix and rtl progression)