libero: add run support

edalize/libero.py

@@ -56,6 +56,16 @@ def get_doc(cls, api_ver):
                         "type": "String",
                         "desc": 'Default HDL (e.g. "VERILOG")',
                     },
+                    {
+                        "name": "programmer",
+                        "type": "String",
+                        "desc": 'Programmer ID (e.g. "E2008ETVQU")',
+                    },
+                    {
+                        "name": "flashpro5_freq",
+                        "type": "Integer",
+                        "desc": "The frequency for jtag communication in Hz",
+                    },
                 ],
             }
 
@@ -75,6 +85,20 @@ def _set_tool_options_defaults(self):
                 )
                 self.tool_options[key] = default_value
 
+    def _run_libero(self, script):
+        if shutil.which("libero"):
+            logger.info(f"Executing Libero TCL Scripts: {script}")
+            return self._run_tool("libero", ["SCRIPT:" + script])
+        else:
+            filePath = os.path.join(
+                Path(self.work_root).relative_to(os.getcwd()), script,
+            )
+            logger.warn(
+                'Libero not found on path, execute manually the script "'
+                + filePath
+                + '"'
+            )
+
     def _check_mandatory_options(self):
         shouldExit = 0
         for key in self.mandatory_options:
@@ -158,6 +182,10 @@ def configure_main(self):
         )
 
         # Render the TCL run file
+        self.render_template(
+            "libero-build.tcl.j2", escaped_name + "-build.tcl", template_vars
+        )
+
         self.render_template(
             "libero-run.tcl.j2", escaped_name + "-run.tcl", template_vars
         )
@@ -169,6 +197,13 @@ def configure_main(self):
 
         logger.info("Cores and Libero TCL Scripts generated.")
 
+        escaped_name = self.name.replace(".", "_")
+        self._run_libero(script=escaped_name + "-project.tcl")
+
+        # FIXME: fusesoc relies on the Makefile timestamp
+        makefile = os.path.join(self.work_root, 'Makefile')
+        open(makefile, 'a').close()
+
     def src_file_filter(self, f):
         file_types = {
             "verilogSource": "-hdl_source {",
@@ -210,19 +245,9 @@ def tim_constraint_file_filter(self, f):
             return f.name
 
     def build_main(self):
-        logger.info("Executing Libero TCL Scripts.")
         escaped_name = self.name.replace(".", "_")
-        if shutil.which("libero"):
-            self._run_tool("libero", ["SCRIPT:" + escaped_name + "-run.tcl"])
-        else:
-            filePath = os.path.join(
-                Path(self.work_root).relative_to(os.getcwd()), escaped_name + "-run.tcl"
-            )
-            logger.warn(
-                'Libero not found on path, execute manually the script "'
-                + filePath
-                + '"'
-            )
+        self._run_libero(script=escaped_name + "-build.tcl")
 
     def run_main(self):
-        pass
+        escaped_name = self.name.replace(".", "_")
+        self._run_libero(script=escaped_name + "-run.tcl")

edalize/templates/libero/libero-build.tcl.j2

@@ -0,0 +1,16 @@
+# This file is generated by Edalize.
+# Microsemi Tcl Script
+# Libero
+
+puts "----------------- Opening project {{name}} ------------------------------"
+open_project -file {{op}}{{prj_root}}/{{name}}.prjx{{cl}}
+
+run_tool -name {SYNTHESIZE}
+run_tool -name {PLACEROUTE}
+run_tool -name {GENERATEPROGRAMMINGDATA}
+
+puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
+puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
+puts "----------------- Finished building project -----------------------------"
+
+close_project -save 1

edalize/templates/libero/libero-project.tcl.j2

@@ -27,7 +27,7 @@ new_project \
 
 {% if incdirs %}
 # Set up the include directories
-set_global_include_path_order -paths "{% for incdir in incdirs %} {{incdir}} {% endfor %}"
+set_global_include_path_order -paths "{% for incdir in incdirs %} ../{{incdir}} {% endfor %}"
 build_design_hierarchy
 {% endif %}
 
@@ -62,9 +62,9 @@ set_root -module {{op}}{{toplevel}}::work{{cl}}
 
 
 
-# Configure Synthesize tool to use the generated Synplify TCL script 
+# Configure Synthesize tool to use the generated Synplify TCL script
 configure_tool -name {SYNTHESIZE} \
-        -params [join "SYNPLIFY_TCL_FILE:" [file join [file dirname [info script]] /{{name}}-syn-user.tcl]]
+        -params [join [list "SYNPLIFY_TCL_FILE" [file join [file dirname [info script]] ./{{name}}-syn-user.tcl]] ":"]
 
 puts "Configured Synthesize tool to use script: {{name}}-syn-user.tcl"
 puts "Configured Synthesize tool to include dirs:"
@@ -122,5 +122,5 @@ organize_tool_files -tool {VERIFYTIMING} \
 
 save_project
 
-puts "If desired, execute the {{name}}-run.tcl script to run the generation flow."
+puts "If desired, execute the {{name}}-build.tcl script to run the generation flow."
 puts "----------------- Finished Importing project -----------------------------"

edalize/templates/libero/libero-run.tcl.j2

@@ -2,12 +2,33 @@
 # Microsemi Tcl Script
 # Libero
 
-source {{op}}{{name}}-project.tcl{{cl}}
+puts "----------------- Opening project {{name}} ------------------------------"
+open_project -file {{op}}{{prj_root}}/{{name}}.prjx{{cl}}
 
-run_tool -name {SYNTHESIZE}
-run_tool -name {PLACEROUTE}
-run_tool -name {GENERATEPROGRAMMINGDATA}
+{% if tool_options.programmer %}
+select_programmer -programmer_id {{op}}{{tool_options.programmer}}{{cl}}
+{% endif %}
 
-puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
-puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
-puts "----------------- Finished building project -----------------------------"
+configure_tool \
+         -name {PROGRAMMER_INFO} \
+         -params {flashpro3_clk_mode:free_running_clk} \
+         -params {flashpro3_force_freq:OFF} \
+         -params {flashpro3_freq:4000000} \
+         -params {flashpro3_vpump:OFF} \
+         -params {flashpro4_clk_mode:free_running_clk} \
+         -params {flashpro4_force_freq:OFF} \
+         -params {flashpro4_freq:4000000} \
+         -params {flashpro4_vpump:OFF} \
+         -params {flashpro5_force_freq:{{ 'ON' if tool_options.flashpro5_freq else 'OFF' }}} \
+         -params {flashpro5_freq:{{ tool_options.flashpro5_freq if tool_options.flashpro5_freq else 4000000 }}} \
+         -params {flashpro5_vpump:OFF} \
+         -params {flashpro6_force_sck_freq:OFF} \
+         -params {flashpro6_force_tck_freq:OFF} \
+         -params {flashpro6_sck_freq:20000000} \
+         -params {flashpro6_tck_freq:4000000} \
+         -params {flashpro6_vpump:OFF}
+
+puts "----------------- Programming device ------------------------------------"
+run_tool -name {PROGRAMDEVICE}
+
+close_project

edalize/templates/libero/libero-syn-user.tcl.j2

@@ -3,14 +3,14 @@
 # Libero
 
 {% if vlogparam -%}{%- for k,v in vlogparam.items() %}
-set_option -hdl_param -set {{k}}={{v}}
+set_option -hdl_param -set {{k}}={{ v|generic_value_str(str_quote_style="\"", bool_is_str=True) }}
 {% endfor -%}{%- endif %}
 {% if vlogdefine -%}{%- for k,v in vlogdefine.items() %}
-set_option -hdl_define -set {{k}}={{v}}
+set_option -hdl_define -set {{k}}={{ v|generic_value_str(str_quote_style="\"", bool_is_str=True) }}
 {% endfor -%}{%- endif %}
 {% if generic -%}
 set_option -hdl_param -set {
-  {%- for k, v in generic.items() %}{{ k }}={{ v|generic_value_str(bool_is_str = True) }} {% endfor -%}
+  {%- for k, v in generic.items() %}{{ k }}={{ v|generic_value_str(str_quote_style="\"", bool_is_str=True) }} {% endfor -%}
   }
 {%- endif %}
 

setup.py

@@ -37,6 +37,7 @@ def read(fname):
             "templates/ascentlint/Makefile.j2",
             "templates/ascentlint/run-ascentlint.tcl.j2",
             "templates/libero/libero-project.tcl.j2",
+            "templates/libero/libero-build.tcl.j2",
             "templates/libero/libero-run.tcl.j2",
             "templates/libero/libero-syn-user.tcl.j2",
             "templates/ghdl/Makefile.j2",

tests/test_libero.py

@@ -12,6 +12,7 @@ def test_libero(make_edalize_test):
     tf.compare_files(
         [
             name + "-project.tcl",
+            name + "-build.tcl",
             name + "-run.tcl",
             name + "-syn-user.tcl",
         ]
@@ -30,6 +31,8 @@ def test_libero_with_params(make_edalize_test):
         "range": "EXT",
         "defiostd": "LVCMOS 1.8V",
         "hdl": "VHDL",
+        "programmer": "E2008ETVQU",
+        "flashpro5_freq": "15000000",
     }
 
     tf = make_edalize_test("libero", test_name=name, tool_options=tool_options)
@@ -38,6 +41,7 @@ def test_libero_with_params(make_edalize_test):
     tf.compare_files(
         [
             name + "-project.tcl",
+            name + "-build.tcl",
             name + "-run.tcl",
             name + "-syn-user.tcl",
         ]

tests/test_libero/libero-test-all-build.tcl

@@ -0,0 +1,13 @@
+# This file is generated by Edalize.
+# Microsemi Tcl Script
+# Libero
+
+source {libero-test-all-project.tcl}
+
+run_tool -name {SYNTHESIZE}
+run_tool -name {PLACEROUTE}
+run_tool -name {GENERATEPROGRAMMINGDATA}
+
+puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
+puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
+puts "----------------- Finished building project -----------------------------"

tests/test_libero/libero-test-all-project.tcl

@@ -50,9 +50,9 @@ set_root -module {top_module::work}
 
 
 
-# Configure Synthesize tool to use the generated Synplify TCL script 
+# Configure Synthesize tool to use the generated Synplify TCL script
 configure_tool -name {SYNTHESIZE} \
-        -params [join "SYNPLIFY_TCL_FILE:" [file join [file dirname [info script]] /libero-test-all-syn-user.tcl]]
+        -params [join [list "SYNPLIFY_TCL_FILE" [file join [file dirname [info script]] ../libero-test-all-syn-user.tcl]] ":"]
 
 puts "Configured Synthesize tool to use script: libero-test-all-syn-user.tcl"
 puts "Configured Synthesize tool to include dirs:"

tests/test_libero/libero-test-all-run.tcl

@@ -2,12 +2,31 @@
 # Microsemi Tcl Script
 # Libero
 
-source {libero-test-all-project.tcl}
+puts "----------------- Opening project libero-test-all ------------------------------"
+open_project -file {./prj/libero-test-all.prjx}
 
-run_tool -name {SYNTHESIZE}
-run_tool -name {PLACEROUTE}
-run_tool -name {GENERATEPROGRAMMINGDATA}
+select_programmer -programmer_id {E2008ETVQU}
 
-puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
-puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
-puts "----------------- Finished building project -----------------------------"
+configure_tool \
+         -name {PROGRAMMER_INFO} \
+         -params {flashpro3_clk_mode:free_running_clk} \
+         -params {flashpro3_force_freq:OFF} \
+         -params {flashpro3_freq:4000000} \
+         -params {flashpro3_vpump:OFF} \
+         -params {flashpro4_clk_mode:free_running_clk} \
+         -params {flashpro4_force_freq:OFF} \
+         -params {flashpro4_freq:4000000} \
+         -params {flashpro4_vpump:OFF} \
+         -params {flashpro5_force_freq:ON} \
+         -params {flashpro5_freq:15000000} \
+         -params {flashpro5_vpump:OFF} \
+         -params {flashpro6_force_sck_freq:OFF} \
+         -params {flashpro6_force_tck_freq:OFF} \
+         -params {flashpro6_sck_freq:20000000} \
+         -params {flashpro6_tck_freq:4000000} \
+         -params {flashpro6_vpump:OFF}
+
+puts "----------------- Programming device ------------------------------------"
+run_tool -name {PROGRAMDEVICE}
+
+close_project

tests/test_libero/libero-test-all-syn-user.tcl

@@ -2,11 +2,11 @@
 # Synplify Tcl Script
 # Libero
 
-set_option -hdl_param -set vlogparam_bool=True
+set_option -hdl_param -set vlogparam_bool=true
 set_option -hdl_param -set vlogparam_int=42
-set_option -hdl_param -set vlogparam_str=hello
-set_option -hdl_define -set vlogdefine_bool=True
+set_option -hdl_param -set vlogparam_str="hello"
+set_option -hdl_define -set vlogdefine_bool=true
 set_option -hdl_define -set vlogdefine_int=42
-set_option -hdl_define -set vlogdefine_str=hello
+set_option -hdl_define -set vlogdefine_str="hello"
 
 set_option -include_path {../../.}

tests/test_libero/libero-test-build.tcl

@@ -0,0 +1,13 @@
+# This file is generated by Edalize.
+# Microsemi Tcl Script
+# Libero
+
+source {libero-test-project.tcl}
+
+run_tool -name {SYNTHESIZE}
+run_tool -name {PLACEROUTE}
+run_tool -name {GENERATEPROGRAMMINGDATA}
+
+puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
+puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
+puts "----------------- Finished building project -----------------------------"

tests/test_libero/libero-test-project.tcl

@@ -47,9 +47,9 @@ set_root -module {top_module::work}
 
 
 
-# Configure Synthesize tool to use the generated Synplify TCL script 
+# Configure Synthesize tool to use the generated Synplify TCL script
 configure_tool -name {SYNTHESIZE} \
-        -params [join "SYNPLIFY_TCL_FILE:" [file join [file dirname [info script]] /libero-test-syn-user.tcl]]
+        -params [join [list "SYNPLIFY_TCL_FILE" [file join [file dirname [info script]] ../libero-test-syn-user.tcl]] ":"]
 
 puts "Configured Synthesize tool to use script: libero-test-syn-user.tcl"
 puts "Configured Synthesize tool to include dirs:"

tests/test_libero/libero-test-run.tcl

@@ -2,12 +2,30 @@
 # Microsemi Tcl Script
 # Libero
 
-source {libero-test-project.tcl}
+puts "----------------- Opening project libero-test ------------------------------"
+open_project -file {./prj/libero-test.prjx}
 
-run_tool -name {SYNTHESIZE}
-run_tool -name {PLACEROUTE}
-run_tool -name {GENERATEPROGRAMMINGDATA}
 
-puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu."
-puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming."
-puts "----------------- Finished building project -----------------------------"
+configure_tool \
+         -name {PROGRAMMER_INFO} \
+         -params {flashpro3_clk_mode:free_running_clk} \
+         -params {flashpro3_force_freq:OFF} \
+         -params {flashpro3_freq:4000000} \
+         -params {flashpro3_vpump:OFF} \
+         -params {flashpro4_clk_mode:free_running_clk} \
+         -params {flashpro4_force_freq:OFF} \
+         -params {flashpro4_freq:4000000} \
+         -params {flashpro4_vpump:OFF} \
+         -params {flashpro5_force_freq:OFF} \
+         -params {flashpro5_freq:4000000} \
+         -params {flashpro5_vpump:OFF} \
+         -params {flashpro6_force_sck_freq:OFF} \
+         -params {flashpro6_force_tck_freq:OFF} \
+         -params {flashpro6_sck_freq:20000000} \
+         -params {flashpro6_tck_freq:4000000} \
+         -params {flashpro6_vpump:OFF}
+
+puts "----------------- Programming device ------------------------------------"
+run_tool -name {PROGRAMDEVICE}
+
+close_project

tests/test_libero/libero-test-syn-user.tcl

@@ -2,11 +2,11 @@
 # Synplify Tcl Script
 # Libero
 
-set_option -hdl_param -set vlogparam_bool=True
+set_option -hdl_param -set vlogparam_bool=true
 set_option -hdl_param -set vlogparam_int=42
-set_option -hdl_param -set vlogparam_str=hello
-set_option -hdl_define -set vlogdefine_bool=True
+set_option -hdl_param -set vlogparam_str="hello"
+set_option -hdl_define -set vlogdefine_bool=true
 set_option -hdl_define -set vlogdefine_int=42
-set_option -hdl_define -set vlogdefine_str=hello
+set_option -hdl_define -set vlogdefine_str="hello"
 
 set_option -include_path {../../.}