Libero Updates

* Add support for Libero netlist constraints

Libero has two types of netlist constraints files that are synthesis
only, so they didn't work with the existing setup. Adding specific
filters for synthesis and place/route simplified the changes needed to
the template.

* Simplify Libero --no-export

Always use `create_links` instead of `import_files` in the Libero
project script to simplify the --no-export implementation.

* Simplify Libero constraints filters

Since we're no longer importing the constraints files, we don't have to
worry about converting the file names to point to the import paths, so
the filters can be much simpler.

---------

Co-authored-by: Paul Gatewood <[email protected]>

edalize/libero.py

@@ -95,7 +95,15 @@ def configure_main(self):
         self._check_mandatory_options()
         (src_files, incdirs) = self._get_fileset_files(force_slash=True)
         self.jinja_env.filters["src_file_filter"] = self.src_file_filter
-        self.jinja_env.filters["constraint_file_filter"] = self.constraint_file_filter
+        self.jinja_env.filters[
+            "syn_constraint_file_filter"
+        ] = self.syn_constraint_file_filter
+        self.jinja_env.filters[
+            "pnr_constraint_file_filter"
+        ] = self.pnr_constraint_file_filter
+        self.jinja_env.filters[
+            "tim_constraint_file_filter"
+        ] = self.tim_constraint_file_filter
         self.jinja_env.filters["tcl_file_filter"] = self.tcl_file_filter
 
         escaped_name = self.name.replace(".", "_")
@@ -168,6 +176,8 @@ def src_file_filter(self, f):
             "PDC": "-io_pdc {",
             "SDC": "-sdc {",
             "FPPDC": "-fp_pdc {",
+            "FDC": "-net_fdc {",
+            "NDC": "-ndc {",
         }
         _file_type = f.file_type.split("-")[0]
         if _file_type in file_types:
@@ -186,20 +196,17 @@ def tcl_file_filter(self, f):
             return file_types[_file_type] + f.name
         return ""
 
-    def constraint_file_filter(self, f, type="ALL"):
-        file_types = {
-            "PDC": "constraint/io/",
-            "SDC": "constraint/",
-            "FPPDC": "constraint/fp/",
-        }
-        _file_type = f.file_type.split("-")[0]
-        if _file_type in file_types:
-            filename = f.name.split("/")[-1]
-            if type == "ALL":
-                return file_types[_file_type] + filename
-            elif _file_type == type:
-                return file_types[_file_type] + filename
-        return ""
+    def syn_constraint_file_filter(self, f):
+        if f.file_type in ["FDC", "NDC", "SDC"]:
+            return f.name
+
+    def pnr_constraint_file_filter(self, f):
+        if f.file_type in ["FPPDC", "PDC", "SDC"]:
+            return f.name
+
+    def tim_constraint_file_filter(self, f):
+        if f.file_type == "SDC":
+            return f.name
 
     def build_main(self):
         logger.info("Executing Libero TCL Scripts.")

edalize/templates/libero/libero-project.tcl.j2

@@ -4,25 +4,44 @@
 
 puts "----------------- Creating project {{name}} ------------------------------"
 # Create a new project with device parameters
-new_project -location {{op}}{{prj_root}}{{cl}} -name {{name}} -project_description {} -hdl {{op}}{{tool_options.hdl}}{{cl}} -family {{op}}{{tool_options.family}}{{cl}} -die {{op}}{{tool_options.die}}{{cl}} -package {{op}}{{tool_options.package}}{{cl}} {% if tool_options.speed -%} -speed {{op}}{{tool_options.speed}}{{cl}}{{sp}}{%- endif %}{% if tool_options.dievoltage -%} -die_voltage {{op}}{{tool_options.dievoltage}}{{cl}}{{sp}}{%- endif %}{% if tool_options.range -%}-part_range {{op}}{{tool_options.range}}{{cl}}{{sp}}{%- endif %}{% if tool_options.defiostd -%} -adv_options {IO_DEFT_STD:{{tool_options.defiostd}}{{cl}}{% endif %}
-
+new_project \
+    -location {{op}}{{prj_root}}{{cl}} \
+    -name {{name}} \
+    -project_description {} \
+    -hdl {{op}}{{tool_options.hdl}}{{cl}} \
+    -family {{op}}{{tool_options.family}}{{cl}} \
+    -die {{op}}{{tool_options.die}}{{cl}} \
+    -package {{op}}{{tool_options.package}}{{cl}} \
+{% if tool_options.speed %}
+    -speed {{op}}{{tool_options.speed}}{{cl}}{{sp}} \
+{% endif %}
+{% if tool_options.dievoltage %}
+    -die_voltage {{op}}{{tool_options.dievoltage}}{{cl}}{{sp}} \
+{% endif %}
+{% if tool_options.range %}
+    -part_range {{op}}{{tool_options.range}}{{cl}}{{sp}} \
+{% endif %}
+{% if tool_options.defiostd %}
+    -adv_options {IO_DEFT_STD:{{tool_options.defiostd}}{{cl}} \
+{% endif %}
 
 {% if incdirs %}
 # Set up the include directories
-set_global_include_path_order -paths "{% for incdir in incdirs %} [file normalize {{incdir}}] {% endfor %}"
+set_global_include_path_order -paths "{% for incdir in incdirs %} {{incdir}} {% endfor %}"
 build_design_hierarchy
 {% endif %}
 
-# Import HDL sources and constraints
+# Link HDL sources and constraints
+create_links \
 {% for src_file in src_files if src_file|src_file_filter%}
-import_files {{src_file|src_file_filter}}{{cl}}
+    {{src_file|src_file_filter}}{{cl}} \
 {% endfor %}
 
 # Import HDL sources on libraries (logical_names)
 {% for library in library_files.items() %}
 {% set lib = library[0] %}
 {% set files = library[1] %}
-import_files \
+create_links \
         -library {{op}}{{lib}}{{cl}} \
         {% for f in files %}
         -hdl_source {{op}}{{f}}{{cl}} \
@@ -53,50 +72,50 @@ puts "Configured Synthesize tool to include dirs:"
 puts "- ../../{{dir}}"
 {% endfor -%}{% endif %}
 
-{% set ns = namespace(SDC=false) %}{# If SDC files are present #}
-{% for src_file in src_files if src_file|constraint_file_filter("SDC") %}
-{% set ns.SDC=true %}
 puts "----------------------- Synthesize Constraints ---------------------------"
-puts "File: {{prj_root}}/{{src_file|constraint_file_filter}}"
+{% set ns = namespace(SYN=false) %}{# If synthesis constraints are present #}
+{% for src_file in src_files if src_file|syn_constraint_file_filter %}
+{% set ns.SYN=true %}
+puts "File: {{src_file|syn_constraint_file_filter}}"
 {% endfor %}
 
-{%- if ns.SDC %}
+{%- if ns.SYN %}
 # Configure Synthesize tool to use the project constraints
 organize_tool_files -tool {SYNTHESIZE} \
-        {% for src_file in src_files if src_file|constraint_file_filter("SDC") %}
-        -file {{op}}{{prj_root}}/{{src_file|constraint_file_filter}}{{cl}} \
+        {% for src_file in src_files if src_file|syn_constraint_file_filter %}
+        -file {{op}}{{src_file|syn_constraint_file_filter}}{{cl}} \
         {% endfor %}
         -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint}
 {% endif %}
 
 # Configure Place and Route tool to use the project constraints
-{% set ns.CNST=false %}
 puts "----------------------- Place and Route Constraints ----------------------"
-{% for src_file in src_files if src_file|constraint_file_filter %}
-{% set ns.CNST=true %}
-puts "File: {{prj_root}}/{{src_file|constraint_file_filter}}"
+{% set ns.PNR=false %}
+{% for src_file in src_files if src_file|pnr_constraint_file_filter %}
+{% set ns.PNR=true %}
+puts "File: {{src_file|pnr_constraint_file_filter}}"
 {% endfor %}
 
-{% if ns.CNST %}
+{% if ns.PNR %}
 organize_tool_files -tool {PLACEROUTE} \
-        {% for src_file in src_files if src_file|constraint_file_filter %}
-        -file {{op}}{{prj_root}}/{{src_file|constraint_file_filter}}{{cl}} \
+        {% for src_file in src_files if src_file|pnr_constraint_file_filter %}
+        -file {{op}}{{src_file|pnr_constraint_file_filter}}{{cl}} \
         {% endfor %}
         -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint}
 {% endif %}
 
-{% if ns.SDC %}
 # Configure Verify Timing tool to use the project constraints
-{% endif %}
-{%- for src_file in src_files if src_file|constraint_file_filter("SDC") %}
 puts "----------------------- Verify Timings Constraints -----------------------"
-puts "File: {{prj_root}}/{{src_file|constraint_file_filter}}"
+{% set ns.TIM=false %}
+{%- for src_file in src_files if src_file|tim_constraint_file_filter %}
+{% set ns.TIM=true %}
+puts "File: {{src_file|tim_constraint_file_filter}}"
 {% endfor %}
 
-{%- if ns.SDC %}
+{%- if ns.TIM %}
 organize_tool_files -tool {VERIFYTIMING} \
-        {% for src_file in src_files if src_file|constraint_file_filter("SDC") %}
-        -file {{op}}{{prj_root}}/{{src_file|constraint_file_filter}}{{cl}} \
+        {% for src_file in src_files if src_file|tim_constraint_file_filter %}
+        -file {{op}}{{src_file|tim_constraint_file_filter}}{{cl}} \
         {% endfor %}
         -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint}
 {% endif %}

tests/test_libero/libero-test-all-project.tcl

@@ -4,25 +4,37 @@
 
 puts "----------------- Creating project libero-test-all ------------------------------"
 # Create a new project with device parameters
-new_project -location {./prj} -name libero-test-all -project_description {} -hdl {VHDL} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V}
+new_project \
+    -location {./prj} \
+    -name libero-test-all \
+    -project_description {} \
+    -hdl {VHDL} \
+    -family {PolarFire} \
+    -die {MPF300TS_ES} \
+    -package {FCG1152} \
+    -speed {-1}  \
+    -die_voltage {1.0}  \
+    -part_range {EXT}  \
+    -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
 
 # Set up the include directories
-set_global_include_path_order -paths " [file normalize .] "
+set_global_include_path_order -paths " . "
 build_design_hierarchy
 
-# Import HDL sources and constraints
-import_files -sdc {sdc_file}
-import_files -hdl_source {sv_file.sv}
-import_files -hdl_source {vlog_file.v}
-import_files -hdl_source {vlog05_file.v}
-import_files -hdl_source {vhdl_file.vhd}
-import_files -hdl_source {vhdl2008_file}
-import_files -hdl_source {another_sv_file.sv}
-import_files -io_pdc {pdc_constraint_file.pdc}
-import_files -fp_pdc {pdc_floorplan_constraint_file.pdc}
+# Link HDL sources and constraints
+create_links \
+    -sdc {sdc_file} \
+    -hdl_source {sv_file.sv} \
+    -hdl_source {vlog_file.v} \
+    -hdl_source {vlog05_file.v} \
+    -hdl_source {vhdl_file.vhd} \
+    -hdl_source {vhdl2008_file} \
+    -hdl_source {another_sv_file.sv} \
+    -io_pdc {pdc_constraint_file.pdc} \
+    -fp_pdc {pdc_floorplan_constraint_file.pdc} \
 
 # Import HDL sources on libraries (logical_names)
-import_files \
+create_links \
         -library {libx} \
         -hdl_source {vhdl_lfile} \
 
@@ -47,29 +59,29 @@ puts "Configured Synthesize tool to include dirs:"
 puts "- ../../."
 
 puts "----------------------- Synthesize Constraints ---------------------------"
-puts "File: ./prj/constraint/sdc_file"
+puts "File: sdc_file"
 # Configure Synthesize tool to use the project constraints
 organize_tool_files -tool {SYNTHESIZE} \
-        -file {./prj/constraint/sdc_file} \
+        -file {sdc_file} \
         -module {top_module::work} -input_type {constraint}
 
 # Configure Place and Route tool to use the project constraints
 puts "----------------------- Place and Route Constraints ----------------------"
-puts "File: ./prj/constraint/sdc_file"
-puts "File: ./prj/constraint/io/pdc_constraint_file.pdc"
-puts "File: ./prj/constraint/fp/pdc_floorplan_constraint_file.pdc"
+puts "File: sdc_file"
+puts "File: pdc_constraint_file.pdc"
+puts "File: pdc_floorplan_constraint_file.pdc"
 
 organize_tool_files -tool {PLACEROUTE} \
-        -file {./prj/constraint/sdc_file} \
-        -file {./prj/constraint/io/pdc_constraint_file.pdc} \
-        -file {./prj/constraint/fp/pdc_floorplan_constraint_file.pdc} \
+        -file {sdc_file} \
+        -file {pdc_constraint_file.pdc} \
+        -file {pdc_floorplan_constraint_file.pdc} \
         -module {top_module::work} -input_type {constraint}
 
 # Configure Verify Timing tool to use the project constraints
 puts "----------------------- Verify Timings Constraints -----------------------"
-puts "File: ./prj/constraint/sdc_file"
+puts "File: sdc_file"
 organize_tool_files -tool {VERIFYTIMING} \
-        -file {./prj/constraint/sdc_file} \
+        -file {sdc_file} \
         -module {top_module::work} -input_type {constraint}
 
 save_project

tests/test_libero/libero-test-project.tcl

@@ -4,25 +4,34 @@
 
 puts "----------------- Creating project libero-test ------------------------------"
 # Create a new project with device parameters
-new_project -location {./prj} -name libero-test -project_description {} -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -part_range {IND} 
+new_project \
+    -location {./prj} \
+    -name libero-test \
+    -project_description {} \
+    -hdl {VERILOG} \
+    -family {PolarFire} \
+    -die {MPF300TS_ES} \
+    -package {FCG1152} \
+    -part_range {IND}  \
 
 # Set up the include directories
-set_global_include_path_order -paths " [file normalize .] "
+set_global_include_path_order -paths " . "
 build_design_hierarchy
 
-# Import HDL sources and constraints
-import_files -sdc {sdc_file}
-import_files -hdl_source {sv_file.sv}
-import_files -hdl_source {vlog_file.v}
-import_files -hdl_source {vlog05_file.v}
-import_files -hdl_source {vhdl_file.vhd}
-import_files -hdl_source {vhdl2008_file}
-import_files -hdl_source {another_sv_file.sv}
-import_files -io_pdc {pdc_constraint_file.pdc}
-import_files -fp_pdc {pdc_floorplan_constraint_file.pdc}
+# Link HDL sources and constraints
+create_links \
+    -sdc {sdc_file} \
+    -hdl_source {sv_file.sv} \
+    -hdl_source {vlog_file.v} \
+    -hdl_source {vlog05_file.v} \
+    -hdl_source {vhdl_file.vhd} \
+    -hdl_source {vhdl2008_file} \
+    -hdl_source {another_sv_file.sv} \
+    -io_pdc {pdc_constraint_file.pdc} \
+    -fp_pdc {pdc_floorplan_constraint_file.pdc} \
 
 # Import HDL sources on libraries (logical_names)
-import_files \
+create_links \
         -library {libx} \
         -hdl_source {vhdl_lfile} \
 
@@ -47,29 +56,29 @@ puts "Configured Synthesize tool to include dirs:"
 puts "- ../../."
 
 puts "----------------------- Synthesize Constraints ---------------------------"
-puts "File: ./prj/constraint/sdc_file"
+puts "File: sdc_file"
 # Configure Synthesize tool to use the project constraints
 organize_tool_files -tool {SYNTHESIZE} \
-        -file {./prj/constraint/sdc_file} \
+        -file {sdc_file} \
         -module {top_module::work} -input_type {constraint}
 
 # Configure Place and Route tool to use the project constraints
 puts "----------------------- Place and Route Constraints ----------------------"
-puts "File: ./prj/constraint/sdc_file"
-puts "File: ./prj/constraint/io/pdc_constraint_file.pdc"
-puts "File: ./prj/constraint/fp/pdc_floorplan_constraint_file.pdc"
+puts "File: sdc_file"
+puts "File: pdc_constraint_file.pdc"
+puts "File: pdc_floorplan_constraint_file.pdc"
 
 organize_tool_files -tool {PLACEROUTE} \
-        -file {./prj/constraint/sdc_file} \
-        -file {./prj/constraint/io/pdc_constraint_file.pdc} \
-        -file {./prj/constraint/fp/pdc_floorplan_constraint_file.pdc} \
+        -file {sdc_file} \
+        -file {pdc_constraint_file.pdc} \
+        -file {pdc_floorplan_constraint_file.pdc} \
         -module {top_module::work} -input_type {constraint}
 
 # Configure Verify Timing tool to use the project constraints
 puts "----------------------- Verify Timings Constraints -----------------------"
-puts "File: ./prj/constraint/sdc_file"
+puts "File: sdc_file"
 organize_tool_files -tool {VERIFYTIMING} \
-        -file {./prj/constraint/sdc_file} \
+        -file {sdc_file} \
         -module {top_module::work} -input_type {constraint}
 
 save_project