create interpreter implementation and adding instruction decoder for riscvi32 #2753
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svv232
commented
Nov 12, 2024
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+603
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+604
| registers[2] = 0x408004f0; | ||
| // set the stack pointer to the top of the stack |
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a follow up pr needs to be made to dynamically set the stack ptr based on the loader, this should be fine for now in the vms memory implementation.
Codecov ReportAttention: Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## master #2753 +/- ##
==========================================
- Coverage 72.07% 71.87% -0.20%
==========================================
Files 255 255
Lines 59110 59263 +153
==========================================
- Hits 42603 42598 -5
- Misses 16507 16665 +158 ☔ View full report in Codecov by Sentry. |
| << 8) | ||
| | (self.get_memory_direct(self.registers.current_instruction_pointer + 3) as u32); | ||
| let instruction = instruction.to_be(); // convert to big endian for more straightforward decoding | ||
| println!( |
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Can we use a debug! instead?
| pub fn decode_instruction(&mut self) -> (Instruction, u32) { | ||
| /* https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf */ | ||
| let instruction = | ||
| ((self.get_memory_direct(self.registers.current_instruction_pointer) as u32) << 24) |
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Could we not avoid to_be below and inverse here the order of the bitshift? like first getting 0, 8, 16 and 24?
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