Chronometer for FPGA chip

####Objective Develop a chronometer (timer) in VHDL for a FPGA chip.

####Implementation The chronometer is divised in 4 major modules :

counter
memory : store the current value of the timer
display with 7-segment display
command circuit : managing the two buttons as a real professional chronometer (with start, pause, turn counter)

####Author Nathan Olff ([email protected])

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
Rapport.pdf		Rapport.pdf
afficheur.vhd		afficheur.vhd
chronometre.vhd		chronometre.vhd
commande.vhd		commande.vhd
commandeParImpulsion.vhd		commandeParImpulsion.vhd
comparEN.vhd		comparEN.vhd
compt10.vhd		compt10.vhd
compteur.vhd		compteur.vhd
div.vhd		div.vhd
impulsionUnique.vhd		impulsionUnique.vhd
memoire.vhd		memoire.vhd
resultat_final.vhd		resultat_final.vhd

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