Fixed bit width in pseudo code for vaeskf1 and vaeskf2

nibrunieAtSi5 · Aug 8, 2023 · 603e231 · 603e231
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diff --git a/doc/vector/insns/vaeskf1.adoc b/doc/vector/insns/vaeskf1.adoc
@@ -95,7 +95,7 @@ function clause execute (VAESKF1(rnd, vd, vs2)) = {
   let r : bits(4) = rnd-1;
 
   foreach (i from eg_start to eg_len-1) {
-      let CurrentRoundKey[3:0]  : bits(32)  = get_velem(vs2, EGW=128, i);
+      let CurrentRoundKey[3:0]  : bits(128)  = get_velem(vs2, EGW=128, i);
       let w[0] : bits(32) = aes_subword_fwd(aes_rotword(CurrentRoundKey[3])) XOR
         aes_decode_rcon(r) XOR CurrentRoundKey[0]
       let w[1] : bits(32) = w[0] XOR CurrentRoundKey[1]

diff --git a/doc/vector/insns/vaeskf2.adoc b/doc/vector/insns/vaeskf2.adoc
@@ -89,7 +89,7 @@ function clause execute (VAESKF2(rnd, vd, vs2)) = {
   eg_start = (vstart/EGS)
 
   foreach (i from eg_start to eg_len-1) {
-      let CurrentRoundKey[3:0]  : bits(32)  = get_velem(vs2, EGW=128, i);
+      let CurrentRoundKey[3:0]  : bits(128)  = get_velem(vs2, EGW=128, i);
       let RoundKeyB[3:0] : bits(32)  = get_velem(vd, EGW=128, i); // Previous round key
 
       let w[0] : bits(32) = if (rnd[0]==1) then

diff --git a/doc/vector/riscv-crypto-spec-vector.adoc b/doc/vector/riscv-crypto-spec-vector.adoc
@@ -2,7 +2,7 @@
 = RISC-V Cryptography Extensions Volume II: Vector Instructions
 :description: The vector cryptography extensions for the RISC-V ISA.
 :company: RISC-V.org
-:revdate: 04 August 2023
+:revdate: 08 August 2023
 :revnumber: v1.0.0
 :revremark: RC2
 :url-riscv: http://riscv.org