Adding support for Xcelium - Xcelium Makefile, README_XCELIUM #9
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mczerski
requested changes
Dec 9, 2020
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| Changes to get the files to run and pass on Xcelium : | ||
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| . In bench/verilog/wb_master_behavioral.v, replace 'return' (match exact case and word) with 'return_type'. As per LRM, 'return' is a SV keyword and cannot be used as a variable name. |
| [Note : A request to make this change to Github Repo for SD Card open source code has been submitted. Check latest file from Github for changes.] | ||
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| . In bench/verilog/sd_controller_top_tb.sv, | ||
| . add `include of all the *.v files (under bench/verilog/) -> sdModel.v, wb_master_behavioral.v, wb_slave_behavioral.v, wb_bus_mon.v, wb_master32.v |
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| . In bench/verilog/sd_controller_top_tb.sv, | ||
| . add `include of all the *.v files (under bench/verilog/) -> sdModel.v, wb_master_behavioral.v, wb_slave_behavioral.v, wb_bus_mon.v, wb_master32.v | ||
| . change the path as -> `define LOG_DIR "../../log", parameter ramdisk="../../bin/ramdisk2.hex", parameter sd_model_log_file="../../log/sd_model.log", parameter wb_memory_file="../../bin/wb_memory.txt" |
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I would preffer to reorganise the directory structure to not to have to change any code for different simulators.
sim/rtl_sim/bin/ should contain only ramdisk2.hex and wb_memory.txt (FLASH.txt is not use so maybe deleted)
sim/rtl_sim/run splitted to sim/rtl_sim/modelsim and sim/rtl_sim/xcelium and should contain simulator specific files. I will update the master branch with those changes for modelsim simulator.
Documentation updated acordingly.
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add doc for Xcelium support and Xcelium Makefile.