End-to-end run. First test.

marianabuhazi · Apr 28, 2024 · 9f25f57 · 9f25f57
1 parent 5b97e7d
commit 9f25f57
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Showing 5 changed files with 54 additions and 9 deletions.
diff --git a/.github/workflows/regression-test.yaml b/.github/workflows/regression-test.yaml
@@ -12,7 +12,11 @@ jobs:
         run: |
           cd $HOME/esp/utils/scripts/actions-pipeline
           ./get_modified_accelerators.sh
-      - name: Run behavioral simulations
+      - name: Run HLS
         run: |
           cd $HOME/esp/utils/scripts/actions-pipeline
           ./run_sims.sh
+      - name: Generate bitstream and program FPGA
+        run: |
+          cd $HOME/esp/utils/scripts/actions-pipeline
+          ./run_esp-config.sh
diff --git a/socs/xilinx-vc707-xc7vx485t/Makefile b/socs/xilinx-vc707-xc7vx485t/Makefile
@@ -44,18 +44,18 @@ TOP_VLOG_SIM_SRCS +=
 
 
 ### Xilinx Vivado hw_server ###
-FPGA_HOST=goliah
+FPGA_HOST=goliah.cs.columbia.edu
 XIL_HW_SERVER_PORT=3132
 
 
 ### Network configuration ###
 
 # IP address or host name of the host connected to the FPGA
-UART_IP=goliah
+UART_IP=goliah.cs.columbia.edu
 UART_PORT=4332
 
 # SSH IP address or host name of the ESP Linux instance or gateway
-SSH_IP=espgate
+SSH_IP=espgate.cs.columbia.edu
 SSH_PORT=5509
 
 # ESPLink IP address or gateway (DO NOT USE HOST NAME)

diff --git a/utils/scripts/actions-pipeline/accelerators.json b/utils/scripts/actions-pipeline/accelerators.json
@@ -1,10 +1,16 @@
 {
 	"accelerators": [
 		{
-		"name": "dummy_stratus",
-		"path": "accelerators/stratus_hls/dummy_stratus",
-		"behavioral": "dummy_stratus-exe",
-		"hls": "dummy_stratus-hls"
+			"name": "cholesky_stratus",
+			"path": "accelerators/stratus_hls/cholesky_stratus",
+			"behavioral": "cholesky_stratus-exe",
+			"hls": "cholesky_stratus-hls"
+		},
+		{
+			"name": "fft2_stratus",
+			"path": "accelerators/stratus_hls/fft2_stratus",
+			"behavioral": "fft2_stratus-exe",
+			"hls": "fft2_stratus-hls"
 		}
 	]
 }

diff --git a/utils/scripts/actions-pipeline/get_hls_accelerators.sh b/utils/scripts/actions-pipeline/get_hls_accelerators.sh
@@ -24,4 +24,9 @@ for accelerator in "${accelerators[@]}"; do
     latest_version="${sorted_versions[-1]}"
 
     latest_versions["$accelerator"]="${latest_version#*_*_}"
+done
+
+echo "Successful HLS work folders:"
+for accelerator in "${!latest_versions[@]}"; do
+    echo "-- $accelerator: ${latest_versions[$accelerator]}"
 done
diff --git a/utils/scripts/actions-pipeline/run_esp-config.sh b/utils/scripts/actions-pipeline/run_esp-config.sh
@@ -2,14 +2,44 @@
 
 source "get_hls_accelerators.sh"
 defconfig="$HOME/esp/socs/defconfig/esp_xilinx-vc707-xc7vx485t_defconfig"
+fpga_program="$HOME/esp/utils/scripts/actions-pipeline/fpga_program.log"
 
 for accelerator in "${!latest_versions[@]}"; do
     accelerator_upper=$(echo "$accelerator" | tr '[:lower:]' '[:upper:]')
-    esp_config="$HOME/esp/utils/scripts/actions-pipeline/.esp_config_$accelerator"
+    esp_config="$HOME/esp/socs/xilinx-vc707-xc7vx485t/socgen/esp/.esp_config"
+	vivado_syn="$HOME/esp/utils/scripts/actions-pipeline/vivado_syn_$accelerator.log"
     cp "$defconfig" "$esp_config"
 
     sed -i "s/CONFIG_DSU_IP = C0A80107/CONGIG_DSU_IP = C0A8011C/" "$esp_config"
     sed -i "s/CONFIG_DSU_ETH = A6A7A0F8043D/CONGIG_DSU_ETH = A6A7A0F80445/" "$esp_config"
     sed -i "s/TILE_1_0 = 2 empty empty 0 0 0/TILE_1_0 = 2 acc $accelerator_upper 0 0 0 ${latest_versions[$accelerator]} 0 sld/" "$esp_config"
     sed -i "s/POWER_1_0 = empty 0 0 0 0 0 0 0 0 0 0 0 0/POWER_1_0 = $accelerator_upper 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0/" "$esp_config"
+
+	cd "$HOME/esp/socs/xilinx-vc707-xc7vx485t"
+	rm top.bit
+	rm -r vivado
+	make clean
+	cat $esp_config
+	make esp-config
+	make vivado-syn &> "$vivado_syn"
+	if [ -s "top.bit" ]; then
+		make soft
+		make fpga-program &> "$fpga_program"
+		if grep -q ERROR "$fpga_program"; then
+        	echo "FPGA PROGRAM FAILED: $accelerator"
+		else
+			echo "FPGA PROGRAM SUCCESS: $accelerator"
+
+		fi
+		rm "$fpga_program"
+	else
+		echo "Bitstream generation failed: $accelerator"
+	fi
+    # Clean up
+    # fi
+	# delete vivado folder and bit file
+	# make clean
+	# if (top.bit exists, make vivado-syn)
+	# make fpga-program
+	# make uart
 done