Initial files

docs/info.md

@@ -9,12 +9,20 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+This is a PE that will have 
+1) ability to do MAC operations
+2) mixed precision support
+3) connect to MxN array
+4) Add register files for each processing elements
+5) control signals that enable a weight stationary dataflow
+    5a) In the processing element, you’d need control signals like WRITE, READ, and ADDR to write data to the regfile, read data from the regfile, and specify the regfile address for the read/write.
+    5b) In the array as a whole, it’d be too complicated to model the data distribution scheme. So instead, just add control signals to determine when a PE is accumulating a temporal partial sum and needs to be sent inputs vs. when a PE is done and needs to have its output transferred to a global buffer.
+6) Adding a run length encoding encoder and decoder module to the PE array control signals to optimise for sparsity.
 
 ## How to test
 
-Explain how to use your project
+Nothing yet so far
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+Nothing so far

info.yaml

@@ -1,29 +1,30 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  title:        "MAC PE"      # Project title
+  author:       "Mariam"      # Your name
+  discord:      "marmareeta"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "MAC PE that will be optimized"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_pe_mariam"  # Your top module name
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "project.v"
+    - "processing_Element.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
+  ui[0]: "Input_0"
+  ui[1]: "Input_1"
   ui[2]: ""
   ui[3]: ""
   ui[4]: ""
@@ -32,7 +33,7 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
+  uo[0]: "PE_Output"
   uo[1]: ""
   uo[2]: ""
   uo[3]: ""

src/project.v

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2024 Your Name
+ * Copyright (c) 2024 Mariam 
  * SPDX-License-Identifier: Apache-2.0
  */
 
 `default_nettype none
 
-module tt_um_example (
+module tt_um_pe_mariam (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path

test/tb.v

@@ -28,7 +28,7 @@ module tb ();
 `endif
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_pe_mariam user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST