Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[darjeeling,sim] Replace DMI DPI to rv_dm with JTAG DPI to toplevel #24758

Open
wants to merge 1 commit into
base: integrated_dev
Choose a base branch
from

Conversation

qmn
Copy link

@qmn qmn commented Oct 9, 2024

Commit 87d5764 brought rv_dm and lc_ctrl to the same debugging crossbar. However, the existing DMI DPI interface interacts only with rv_dm. Swap this out for the JTAG DPI interface so we can talk to both modules.

I really wanted to also support the old infrastructure, allowing folks to use dmidpi to talk directly (and exclusively) to rv_dm for better performance. But I couldn't find a clean way to do this: the old functionality was gated off by the DMIDirectTAP Verilog define, but as far as I can tell, FuseSoC will always define the Verilog macro, so using this Verilog `ifdef won't work, as the `else block will never be triggered (and Verilog lacks the #if that exists for the C preprocessor):

`ifdef DMIDirectTAP
// OpenOCD direct DMI TAP
bind rv_dm dmidpi u_dmidpi (
.clk_i,
.rst_ni,
.dmi_req_valid,
.dmi_req_ready,
.dmi_req_addr (dmi_req.addr),
.dmi_req_op (dmi_req.op),
.dmi_req_data (dmi_req.data),
.dmi_rsp_valid,
.dmi_rsp_ready,
.dmi_rsp_data (dmi_rsp.data),
.dmi_rsp_resp (dmi_rsp.resp),
.dmi_rst_n (dmi_rst_n)
);
`else
// TODO: this is currently not supported.
// connect this to the correct pins once pinout is final and once the
// verilator testbench supports DFT/Debug strap sampling.
// See also #5221.
//
// jtagdpi u_jtagdpi (
// .clk_i,
// .rst_ni,
// .jtag_tck (cio_jtag_tck),
// .jtag_tms (cio_jtag_tms),
// .jtag_tdi (cio_jtag_tdi),
// .jtag_tdo (cio_jtag_tdo),
// .jtag_trst_n (cio_jtag_trst_n),
// .jtag_srst_n (cio_jtag_srst_n)
// );
`endif

Making it a Verilog parameter might let it look like this:

module chip_sim_tb # (
  parameter bit DMIDirectTAP = 0
)
   ...

  generate if (DMIDirectTAP)
    // instantiate the DMI DPI module
  else
    // instantiate the JTAG DPI module
  endgenerate

But this caused two problems: 1) I'd have to punch a signal from toplevel all the way to rv_dm, which feels clumsy, but the bigger problem was 2) Verilator seems to instantiate both DPI modules, which caused OpenOCD to play poorly when trying to connect to the bitbang port.

This PR is a little more bold in that it eliminates the DMI DPI interface entirely. I'd sincerely appreciate comments on the best way to proceed from here.

Commit 87d5764 brought rv_dm and lc_ctrl to the same debugging
crossbar. However, the existing DMI DPI interface interacts only
with rv_dm. Swap this out for the JTAG DPI interface so we can
talk to both modules.
@qmn qmn requested review from a team and vogelpi as code owners October 9, 2024 19:31
@qmn qmn requested review from hcallahan-lowrisc and removed request for a team October 9, 2024 19:31
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant