[SPI,dv] Remove 30MHz SCK usage when not using two_stages_full_cycle … #24601
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sha-ron
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I'm not sure this is the right way to make the change: you end up not testing 30MHz SCK even when read_pipeline_mode has a value that would allow it.
Is it possible to change the code at the bottom of body so that it skips frequencies that aren't supported (by looking to see how read_pipeline_mode is currently configured)?
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Thank you for the review @rswarbrick. |
…read pipeline Signed-off-by: Sharon Topaz <[email protected]> [SPI,dv] For GLS remove 30MHz SCK usage when not using two_stages_full_cycle read pipeline Signed-off-by: Sharon Topaz <[email protected]>
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I think this fix (using ifndef GATE_LEVEL) is fine as a stopgap solution.
@antmarzam and myself will look at modifying this test / adding a new test to cover #24597, at which point we can come back and remove this.
| @@ -14,7 +14,11 @@ class chip_sw_spi_passthrough_vseq extends chip_sw_base_vseq; | |||
| // Frequencies to use for testing the sequences. | |||
| time sck_periods_ps[] = '{ | |||
| 41_000, // 24 MHz | |||
| `ifndef GATE_LEVEL | |||
| //TODO return 30MHz for GLS simulation when issue #24597 is fixed | |||
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Nit. Project standard syntax for TODOs would be // TODO(#24597) here.
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Thanks @hcallahan-lowrisc for your review, and for looking into this together with @antmarzam . I'll now merge the PR and cherry-pick it over to earlgrey_1.0.0 together with some other changes. Once the real solution is there, we can also merge and cherry-pick it over. |
vogelpi
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…read pipeline.
SCK frequency bigger than 24MHz is supported only when CMD_INFO.read_pipeline_mode is set to 0x2.
Currently the test is using CMD_INFO.read_pipeline_mode=0x0.