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[earlgrey_es] Cherry-pick to earlgrey_es #19703

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Sep 19, 2023
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6 changes: 4 additions & 2 deletions hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
Original file line number Diff line number Diff line change
Expand Up @@ -824,8 +824,10 @@ class flash_ctrl_otf_base_vseq extends flash_ctrl_base_vseq;
if (cfg.scb_h.ecc_error_addr.exists({tl_addr[31:3],3'h0}) | derr_is_set) derr = 1;
end
cfg.otf_read_entry.insert(rd_entry, flash_op);
`uvm_info("direct_read", $sformatf("num_i:%0d bank:%0d exec: 0x%x derr:%0d in_err:%0d",
i, bank, tl_addr, derr, in_err), UVM_MEDIUM)
`uvm_info("direct_read", $sformatf({"num_i:%0d bank:%0d exec: page:%0d(%0d)",
" 0x%x derr:%0d in_err:%0d"},
i, bank, tl_addr, page, (page % 256),
derr, in_err), UVM_MEDIUM)
if (in_err) cfg.scb_h.in_error_addr[{tl_addr[31:3],3'h0}] = 1;

derr |= in_err;
Expand Down
13 changes: 9 additions & 4 deletions hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv
Original file line number Diff line number Diff line change
Expand Up @@ -570,9 +570,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg)
// as correctable ECC errors.
// Only check the first 16 bits because if ECC readout detects uncorrectable error, it
// won't continue read the remaining 16 bits.
`DV_CHECK_EQ(item.d_data & 16'hffff, read_out & 16'hffff,
$sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h",
csr_addr, dai_addr))
uncorr_comp(item.d_data[15:0], read_out[15:0], csr_addr, dai_addr);
end
end else if (ecc_err == OtpNoEccErr) begin
`DV_CHECK_EQ(item.d_data, otp_a[otp_addr],
Expand Down Expand Up @@ -1362,5 +1360,12 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg)
exp_alert = alert_name == "fatal_check_error" ? OtpCheckAlert : OtpMacroAlert;
super.set_exp_alert(alert_name, is_fatal, max_delay);
endfunction

// Compare uncorrectable errored data.
// This function will be overridden by closed source environment.
virtual function void uncorr_comp(bit[15:0] rcv, bit[15:0] exp,
bit [TL_AW-1:0] csr_addr, bit [TL_AW-1:0] dai_addr);
`DV_CHECK_EQ(rcv, exp,
$sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h",
csr_addr, dai_addr))
endfunction
endclass
4 changes: 2 additions & 2 deletions hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1096,7 +1096,7 @@ class chip_sw_base_vseq extends chip_base_vseq;
@(cfg.clk_rst_vif.cb);
uvm_hdl_read(mypath, rma_wipe_idx);
end while (rma_wipe_idx != 3'h3);,
"waiting for rma index = 3", 50_000_000
"waiting for rma index = 3", 100_000_000
)

// Reduce page size to 'd2
Expand All @@ -1110,7 +1110,7 @@ class chip_sw_base_vseq extends chip_base_vseq;
@(cfg.clk_rst_vif.cb);
uvm_hdl_read(mypath, rma_ack);
end while (rma_ack != lc_ctrl_pkg::On);,
"waiting for rma ack == On", 80_000_000
"waiting for rma ack == On", 120_000_000
)
mypath = {path, ".end_page"};
`DV_CHECK(uvm_hdl_release(mypath));
Expand Down
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