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[clkmgr] Deglitch shadow storage error for remaining clock domains
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Signed-off-by: Andreas Kurth <[email protected]>
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@andreaskurth
andreaskurth committed Sep 16, 2024
1 parent 87b9ebb commit ad28822
Showing 1 changed file with 114 additions and 18 deletions.
132 changes: 114 additions & 18 deletions hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1288,7 +1288,18 @@ module clkmgr_reg_top (
io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen;
// F[hi]: 9:0
logic async_io_meas_ctrl_shadowed_hi_err_update;
logic async_io_meas_ctrl_shadowed_hi_err_storage;
logic async_io_meas_ctrl_shadowed_hi_err_storage, deglitched_io_meas_ctrl_shadowed_hi_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_io_i),
.rst_ni(rst_io_ni),
.d_i (async_io_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_io_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1297,11 +1308,12 @@ module clkmgr_reg_top (
) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_io_meas_ctrl_shadowed_hi_err_storage),
.q_o(io_meas_ctrl_shadowed_hi_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_meas_ctrl_shadowed_hi_err_update_sync (
.clk_src_i(clk_io_i),
.rst_src_ni(rst_io_ni),
Expand Down Expand Up @@ -1347,7 +1359,18 @@ module clkmgr_reg_top (

// F[lo]: 19:10
logic async_io_meas_ctrl_shadowed_lo_err_update;
logic async_io_meas_ctrl_shadowed_lo_err_storage;
logic async_io_meas_ctrl_shadowed_lo_err_storage, deglitched_io_meas_ctrl_shadowed_lo_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_io_i),
.rst_ni(rst_io_ni),
.d_i (async_io_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_io_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1356,11 +1379,12 @@ module clkmgr_reg_top (
) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_io_meas_ctrl_shadowed_lo_err_storage),
.q_o(io_meas_ctrl_shadowed_lo_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_meas_ctrl_shadowed_lo_err_update_sync (
.clk_src_i(clk_io_i),
.rst_src_ni(rst_io_ni),
Expand Down Expand Up @@ -1446,7 +1470,18 @@ module clkmgr_reg_top (
io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen;
// F[hi]: 8:0
logic async_io_div2_meas_ctrl_shadowed_hi_err_update;
logic async_io_div2_meas_ctrl_shadowed_hi_err_storage;
logic async_io_div2_meas_ctrl_shadowed_hi_err_storage, deglitched_io_div2_meas_ctrl_shadowed_hi_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:1473 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_div2_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_io_div2_i),
.rst_ni(rst_io_div2_ni),
.d_i (async_io_div2_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_io_div2_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1455,11 +1490,12 @@ module clkmgr_reg_top (
) u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_div2_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_io_div2_meas_ctrl_shadowed_hi_err_storage),
.q_o(io_div2_meas_ctrl_shadowed_hi_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_div2_meas_ctrl_shadowed_hi_err_update_sync (
.clk_src_i(clk_io_div2_i),
.rst_src_ni(rst_io_div2_ni),
Expand Down Expand Up @@ -1505,7 +1541,18 @@ module clkmgr_reg_top (

// F[lo]: 17:9
logic async_io_div2_meas_ctrl_shadowed_lo_err_update;
logic async_io_div2_meas_ctrl_shadowed_lo_err_storage;
logic async_io_div2_meas_ctrl_shadowed_lo_err_storage, deglitched_io_div2_meas_ctrl_shadowed_lo_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:1544 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_div2_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_io_div2_i),
.rst_ni(rst_io_div2_ni),
.d_i (async_io_div2_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_io_div2_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1514,11 +1561,12 @@ module clkmgr_reg_top (
) u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_div2_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_io_div2_meas_ctrl_shadowed_lo_err_storage),
.q_o(io_div2_meas_ctrl_shadowed_lo_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_div2_meas_ctrl_shadowed_lo_err_update_sync (
.clk_src_i(clk_io_div2_i),
.rst_src_ni(rst_io_div2_ni),
Expand Down Expand Up @@ -1604,7 +1652,18 @@ module clkmgr_reg_top (
io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen;
// F[hi]: 7:0
logic async_io_div4_meas_ctrl_shadowed_hi_err_update;
logic async_io_div4_meas_ctrl_shadowed_hi_err_storage;
logic async_io_div4_meas_ctrl_shadowed_hi_err_storage, deglitched_io_div4_meas_ctrl_shadowed_hi_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:1655 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_div4_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_io_div4_i),
.rst_ni(rst_io_div4_ni),
.d_i (async_io_div4_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_io_div4_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1613,11 +1672,12 @@ module clkmgr_reg_top (
) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_io_div4_meas_ctrl_shadowed_hi_err_storage),
.q_o(io_div4_meas_ctrl_shadowed_hi_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync (
.clk_src_i(clk_io_div4_i),
.rst_src_ni(rst_io_div4_ni),
Expand Down Expand Up @@ -1663,7 +1723,18 @@ module clkmgr_reg_top (

// F[lo]: 15:8
logic async_io_div4_meas_ctrl_shadowed_lo_err_update;
logic async_io_div4_meas_ctrl_shadowed_lo_err_storage;
logic async_io_div4_meas_ctrl_shadowed_lo_err_storage, deglitched_io_div4_meas_ctrl_shadowed_lo_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:1726 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_div4_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_io_div4_i),
.rst_ni(rst_io_div4_ni),
.d_i (async_io_div4_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_io_div4_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1672,11 +1743,12 @@ module clkmgr_reg_top (
) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_io_div4_meas_ctrl_shadowed_lo_err_storage),
.q_o(io_div4_meas_ctrl_shadowed_lo_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync (
.clk_src_i(clk_io_div4_i),
.rst_src_ni(rst_io_div4_ni),
Expand Down Expand Up @@ -1787,7 +1859,7 @@ module clkmgr_reg_top (
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync (
.clk_src_i(clk_main_i),
.rst_src_ni(rst_main_ni),
Expand Down Expand Up @@ -1858,7 +1930,7 @@ module clkmgr_reg_top (
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync (
.clk_src_i(clk_main_i),
.rst_src_ni(rst_main_ni),
Expand Down Expand Up @@ -1943,7 +2015,18 @@ module clkmgr_reg_top (
usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen;
// F[hi]: 8:0
logic async_usb_meas_ctrl_shadowed_hi_err_update;
logic async_usb_meas_ctrl_shadowed_hi_err_storage;
logic async_usb_meas_ctrl_shadowed_hi_err_storage, deglitched_usb_meas_ctrl_shadowed_hi_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:2018 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_usb_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_usb_i),
.rst_ni(rst_usb_ni),
.d_i (async_usb_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_usb_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -1952,11 +2035,12 @@ module clkmgr_reg_top (
) u_usb_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_usb_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_usb_meas_ctrl_shadowed_hi_err_storage),
.q_o(usb_meas_ctrl_shadowed_hi_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_usb_meas_ctrl_shadowed_hi_err_update_sync (
.clk_src_i(clk_usb_i),
.rst_src_ni(rst_usb_ni),
Expand Down Expand Up @@ -2002,7 +2086,18 @@ module clkmgr_reg_top (

// F[lo]: 17:9
logic async_usb_meas_ctrl_shadowed_lo_err_update;
logic async_usb_meas_ctrl_shadowed_lo_err_storage;
logic async_usb_meas_ctrl_shadowed_lo_err_storage, deglitched_usb_meas_ctrl_shadowed_lo_err_storage;

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[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"./hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv" range:{start:{line:2089 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_usb_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_usb_i),
.rst_ni(rst_usb_ni),
.d_i (async_usb_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_usb_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -2011,11 +2106,12 @@ module clkmgr_reg_top (
) u_usb_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_usb_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_usb_meas_ctrl_shadowed_lo_err_storage),
.q_o(usb_meas_ctrl_shadowed_lo_storage_err)
);

// update error is transient and must be immediately captured
// prim_pulse_sync flops update_err before sending it across CDC
prim_pulse_sync u_usb_meas_ctrl_shadowed_lo_err_update_sync (
.clk_src_i(clk_usb_i),
.rst_src_ni(rst_usb_ni),
Expand Down

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