[dv/rom/lc] Add some delay after reset in lc_raw_unlock_vseq

Signed-off-by: Eitan Shapira <[email protected]>
lowRISC · Oct 4, 2023 · 7dd6bc4 · 7dd6bc4
1 parent 94c9e37
commit 7dd6bc4
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv
@@ -70,6 +70,9 @@ class chip_sw_lc_raw_unlock_vseq extends chip_sw_base_vseq;
     jtag_lc_state_transition(DecLcStRaw, DecLcStTestUnlocked0);
     // Complete state transition
     apply_reset();
+    // Needed to add extra delay between the reset and the JTAG read of the lc_ctrl status
+    // register.
+    #(10us);
     wait_lc_ready();
 
     // After reset, clock bypass back to 'off'.