Merge branch 'devel'

build.gradle

@@ -26,7 +26,7 @@ allprojects {
         properties {
             property "sonar.projectKey", "br.com.lnls.dig.halcs"
             property "sonar.projectName", "HALCS Hardware Abstraction Layer for Control Systems"
-            property "sonar.projectVersion", "v0.5"
+            property "sonar.projectVersion", "v1.0.0"
 
             property "sonar.links.homepage", "https://github.com/lnls-dig/halcs"
             property "sonar.links.ci", "https://travis-ci.org/lnls-dig/halcs"

compile.sh

@@ -104,7 +104,7 @@ fi
 
 # Select if we want to have the AFCv3 DDR memory shrink to 2^28 or the full size 2^32. Options are: (y)es ot (n)o.
 # This is a TEMPORARY fix until the AFCv3 FPGA firmware is fixed. If unsure, select (y)es.
-SHRINK_AFCV3_DDR_SIZE=y
+SHRINK_AFCV3_DDR_SIZE=n
 #Select if we want to compile code with all messages outputs. Options are: y(es) or n(o)
 LOCAL_MSG_DBG=n
 #Select if we want to compile with debug mode on. Options are: y(es) or n(o)

core/common/include/hw/wb_afc_mgmt_regs.h

@@ -0,0 +1,56 @@
+/*
+  Register definitions for slave core: AFC MGMT registers
+
+  * File           : wb_afc_mgmt_regs.h
+  * Author         : auto-generated by wbgen2 from afc_mgmt_regs.wb
+  * Created        : Fri Aug 25 16:13:48 2017
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE afc_mgmt_regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_AFC_MGMT_REGS_WB
+#define __WBGEN2_REGDEFS_AFC_MGMT_REGS_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Clock distribution control register */
+
+/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
+#define AFC_MGMT_CLK_DISTRIB_SI57X_OE         WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Reserved in reg: Clock distribution control register */
+#define AFC_MGMT_CLK_DISTRIB_RESERVED_MASK    WBGEN2_GEN_MASK(1, 31)
+#define AFC_MGMT_CLK_DISTRIB_RESERVED_SHIFT   1
+#define AFC_MGMT_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 1, 31)
+#define AFC_MGMT_CLK_DISTRIB_RESERVED_R(reg)  WBGEN2_GEN_READ(reg, 1, 31)
+
+/* definitions for register: Dummy */
+
+/* definitions for field: Reserved in reg: Dummy */
+#define AFC_MGMT_DUMMY_RESERVED_MASK          WBGEN2_GEN_MASK(0, 32)
+#define AFC_MGMT_DUMMY_RESERVED_SHIFT         0
+#define AFC_MGMT_DUMMY_RESERVED_W(value)      WBGEN2_GEN_WRITE(value, 0, 32)
+#define AFC_MGMT_DUMMY_RESERVED_R(reg)        WBGEN2_GEN_READ(reg, 0, 32)
+/* [0x0]: REG Clock distribution control register */
+#define AFC_MGMT_REG_CLK_DISTRIB 0x00000000
+/* [0x4]: REG Dummy */
+#define AFC_MGMT_REG_DUMMY 0x00000004
+#endif

core/common/include/hw/wb_tim_rcv_core_regs.h

@@ -0,0 +1,99 @@
+/*
+  Register definitions for slave core: Timing Receiver Core registers
+
+  * File           : wb_tim_rcv_core_regs.h
+  * Author         : auto-generated by wbgen2 from tim_rcv_core.wb
+  * Created        : Mon Aug 28 13:38:10 2017
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tim_rcv_core.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_TIM_RCV_CORE_WB
+#define __WBGEN2_REGDEFS_TIM_RCV_CORE_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Phase Measurement Control register */
+
+/* definitions for register: DMTD A Control register */
+
+/* definitions for field: Deglitcher Threshold in reg: DMTD A Control register */
+#define TIM_RCV_CORE_DMTD_A_CTL_DEGLITCHER_THRES_MASK WBGEN2_GEN_MASK(0, 16)
+#define TIM_RCV_CORE_DMTD_A_CTL_DEGLITCHER_THRES_SHIFT 0
+#define TIM_RCV_CORE_DMTD_A_CTL_DEGLITCHER_THRES_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define TIM_RCV_CORE_DMTD_A_CTL_DEGLITCHER_THRES_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Reserved1 in reg: DMTD A Control register */
+#define TIM_RCV_CORE_DMTD_A_CTL_RESERVED1_MASK WBGEN2_GEN_MASK(16, 16)
+#define TIM_RCV_CORE_DMTD_A_CTL_RESERVED1_SHIFT 16
+#define TIM_RCV_CORE_DMTD_A_CTL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define TIM_RCV_CORE_DMTD_A_CTL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: DMTD B Control register */
+
+/* definitions for field: Deglitcher Threshold in reg: DMTD B Control register */
+#define TIM_RCV_CORE_DMTD_B_CTL_DEGLITCHER_THRES_MASK WBGEN2_GEN_MASK(0, 16)
+#define TIM_RCV_CORE_DMTD_B_CTL_DEGLITCHER_THRES_SHIFT 0
+#define TIM_RCV_CORE_DMTD_B_CTL_DEGLITCHER_THRES_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define TIM_RCV_CORE_DMTD_B_CTL_DEGLITCHER_THRES_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Reserved1 in reg: DMTD B Control register */
+#define TIM_RCV_CORE_DMTD_B_CTL_RESERVED1_MASK WBGEN2_GEN_MASK(16, 16)
+#define TIM_RCV_CORE_DMTD_B_CTL_RESERVED1_SHIFT 16
+#define TIM_RCV_CORE_DMTD_B_CTL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
+#define TIM_RCV_CORE_DMTD_B_CTL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Averaged Phase Difference Measurement */
+
+/* definitions for register: DMTD A input clock Frequency */
+
+/* definitions for field: Frequency in reg: DMTD A input clock Frequency */
+#define TIM_RCV_CORE_F_DMTD_A_FREQ_MASK       WBGEN2_GEN_MASK(0, 28)
+#define TIM_RCV_CORE_F_DMTD_A_FREQ_SHIFT      0
+#define TIM_RCV_CORE_F_DMTD_A_FREQ_W(value)   WBGEN2_GEN_WRITE(value, 0, 28)
+#define TIM_RCV_CORE_F_DMTD_A_FREQ_R(reg)     WBGEN2_GEN_READ(reg, 0, 28)
+
+/* definitions for field: Valid in reg: DMTD A input clock Frequency */
+#define TIM_RCV_CORE_F_DMTD_A_VALID           WBGEN2_GEN_MASK(28, 1)
+
+/* definitions for register: DMTD B input clock Frequency */
+
+/* definitions for field: Frequency in reg: DMTD B input clock Frequency */
+#define TIM_RCV_CORE_F_DMTD_B_FREQ_MASK       WBGEN2_GEN_MASK(0, 28)
+#define TIM_RCV_CORE_F_DMTD_B_FREQ_SHIFT      0
+#define TIM_RCV_CORE_F_DMTD_B_FREQ_W(value)   WBGEN2_GEN_WRITE(value, 0, 28)
+#define TIM_RCV_CORE_F_DMTD_B_FREQ_R(reg)     WBGEN2_GEN_READ(reg, 0, 28)
+
+/* definitions for field: Valid in reg: DMTD B input clock Frequency */
+#define TIM_RCV_CORE_F_DMTD_B_VALID           WBGEN2_GEN_MASK(28, 1)
+/* [0x0]: REG Phase Measurement Control register */
+#define TIM_RCV_CORE_REG_PHASE_MEAS_NAVG 0x00000000
+/* [0x4]: REG DMTD A Control register */
+#define TIM_RCV_CORE_REG_DMTD_A_CTL 0x00000004
+/* [0x8]: REG DMTD B Control register */
+#define TIM_RCV_CORE_REG_DMTD_B_CTL 0x00000008
+/* [0xc]: REG Averaged Phase Difference Measurement */
+#define TIM_RCV_CORE_REG_PHASE_MEAS 0x0000000c
+/* [0x10]: REG DMTD A input clock Frequency */
+#define TIM_RCV_CORE_REG_F_DMTD_A 0x00000010
+/* [0x14]: REG DMTD B input clock Frequency */
+#define TIM_RCV_CORE_REG_F_DMTD_B 0x00000014
+#endif

core/common/include/mem_layout_common.h

@@ -29,7 +29,7 @@ extern "C" {
 
 /* DSP Components */
 #define DSP_CTRL_RAW_REGS_OFFS                      0x0000
-#define DSP_HALCS_RAW_SWAP_OFFS                       0x0100
+#define DSP_HALCS_RAW_SWAP_OFFS                     0x0100
 
 /* AFC DIAG Components */
 #define WB_AFC_DIAG_CTRL_RAW_REGS_OFFS              0x0000
@@ -43,6 +43,13 @@ extern "C" {
 /* Trigger Mux Components */
 #define WB_TRIGGER_MUX_RAW_REG_OFFS                 0x0000
 
+/* AFC MGMT Component */
+#define AFC_MGMT_CTRL_RAW_REGS_OFFS                 0x0000
+#define AFC_MGMT_SI57X_RAW_I2C_OFFS                 0x0100
+
+/* Timing Receiver Component */
+#define TIM_RCV_RAW_REGS_OFFS                       0x0000
+
 /* Large Memory RAW Addresses. It lives at address 0 */
 #define LARGE_MEM_RAW_ADDR                          0x00000000
 
@@ -79,6 +86,13 @@ extern "C" {
 /* Trigger Mux Components */
 #define WB_TRIGGER_MUX_REG_OFFS                     (WB_TRIGGER_MUX_RAW_REG_OFFS)
 
+/* AFC_MGMT Component */
+#define AFC_MGMT_CTRL_REGS_OFFS                     (AFC_MGMT_CTRL_RAW_REGS_OFFS)
+#define AFC_MGMT_SI57X_I2C_OFFS                     (AFC_MGMT_SI57X_RAW_I2C_OFFS)
+
+/* Timing Receiver Component */
+#define TIM_RCV_REGS_OFFS                           (TIM_RCV_RAW_REGS_OFFS)
+
 /* The following is a bit of a hack.
  * We employ a generic API for talking to the hardware.
  * So, our transport layer (PCIe or Ethernet, for now)

core/sm_io/include/sm_io_afc_mgmt_codes.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 LNLS (www.lnls.br)
+ * Author: Lucas Russo <[email protected]>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_AFC_MGMT_CODES_H_
+#define _SM_IO_AFC_MGMT_CODES_H_
+
+/* Messaging OPCODES */
+#define AFC_MGMT_OPCODE_TYPE                         uint32_t
+#define AFC_MGMT_OPCODE_SIZE                         (sizeof (AFC_MGMT_OPCODE_TYPE))
+
+/* FIXME: Reuse FMC_ACTIVE_CLOCK codes so we can use the same
+ * client functions */
+#define AFC_MGMT_OPCODE_SI57X_OE                     0
+#define AFC_MGMT_NAME_SI57X_OE                       "fmc_active_clk_si57x_oe"
+#define AFC_MGMT_OPCODE_SI57X_FREQ                   14
+#define AFC_MGMT_NAME_SI57X_FREQ                     "fmc_active_clk_si57x_freq"
+#define AFC_MGMT_OPCODE_SI57X_GET_DEFAULTS           15
+#define AFC_MGMT_NAME_SI57X_GET_DEFAULTS             "fmc_active_clk_si57x_get_defaults"
+#define AFC_MGMT_OPCODE_SI57X_FSTARTUP               19
+#define AFC_MGMT_NAME_SI57X_FSTARTUP                 "fmc_active_clk_si57x_fstartup"
+#define AFC_MGMT_OPCODE_END                          20
+
+/* Messaging Reply OPCODES */
+#define AFC_MGMT_REPLY_TYPE                          uint32_t
+#define AFC_MGMT_REPLY_SIZE                          (sizeof (AFC_MGMT_REPLY_TYPE))
+
+#define AFC_MGMT_OK                                  0   /* Operation was successful */
+#define AFC_MGMT_ERR                                 1   /* Could not set/get value */
+#define AFC_MGMT_UNINPL                              2   /* Unimplemented function or operation */
+#define AFC_MGMT_REPLY_END                           3   /* End marker */
+
+#endif

core/sm_io/include/sm_io_tim_rcv_codes.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2017 LNLS (www.lnls.br)
+ * Author: Lucas Russo <[email protected]>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#ifndef _SM_IO_TIM_RCV_CODES_H_
+#define _SM_IO_TIM_RCV_CODES_H_
+
+#include <inttypes.h>
+
+/* Messaging OPCODES */
+#define TIM_RCV_OPCODE_TYPE                          uint32_t
+#define TIM_RCV_OPCODE_SIZE                          (sizeof (TIM_RCV_OPCODE_TYPE))
+
+#define TIM_RCV_OPCODE_PHASE_MEAS_NAVG               0
+#define TIM_RCV_NAME_PHASE_MEAS_NAVG                 "tim_rcv_phase_meas_navg"
+#define TIM_RCV_OPCODE_DMTD_A_DEGLITCHER_THRES       1
+#define TIM_RCV_NAME_DMTD_A_DEGLITCHER_THRES         "tim_rcv_dmtd_a_deglitcher_thres"
+#define TIM_RCV_OPCODE_DMTD_B_DEGLITCHER_THRES       2
+#define TIM_RCV_NAME_DMTD_B_DEGLITCHER_THRES         "tim_rcv_dmtd_b_deglitcher_thres"
+#define TIM_RCV_OPCODE_PHASE_MEAS                    3
+#define TIM_RCV_NAME_PHASE_MEAS                      "tim_rcv_phase_meas"
+#define TIM_RCV_OPCODE_DMTD_A_FREQ                   4
+#define TIM_RCV_NAME_DMTD_A_FREQ                     "tim_rcv_dmtd_a_freq"
+#define TIM_RCV_OPCODE_DMTD_A_VALID                  5
+#define TIM_RCV_NAME_DMTD_A_VALID                    "tim_rcv_dmtd_a_valid"
+#define TIM_RCV_OPCODE_DMTD_B_FREQ                   6
+#define TIM_RCV_NAME_DMTD_B_FREQ                     "tim_rcv_dmtd_b_freq"
+#define TIM_RCV_OPCODE_DMTD_B_VALID                  7
+#define TIM_RCV_NAME_DMTD_B_VALID                    "tim_rcv_dmtd_b_valid"
+#define TIM_RCV_OPCODE_END                           8
+
+/* Messaging Reply OPCODES */
+#define AFC_MGMT_REPLY_TYPE                          uint32_t
+#define AFC_MGMT_REPLY_SIZE                          (sizeof (AFC_MGMT_REPLY_TYPE))
+
+#define AFC_MGMT_OK                                  0   /* Operation was successful */
+#define AFC_MGMT_ERR                                 1   /* Could not set/get value */
+#define AFC_MGMT_UNINPL                              2   /* Unimplemented function or operation */
+#define AFC_MGMT_REPLY_END                           3   /* End marker */
+
+#endif
+

core/sm_io/src/sm_io/c/modules/afc_mgmt/afc_mgmt.mk

@@ -0,0 +1,5 @@
+sm_io_afc_mgmt_DIR = $(sm_io_modules_DIR)/afc_mgmt
+
+sm_io_afc_mgmt_OBJS = $(sm_io_afc_mgmt_DIR)/sm_io_afc_mgmt_core.o \
+				$(sm_io_afc_mgmt_DIR)/sm_io_afc_mgmt_exp.o \
+				$(sm_io_afc_mgmt_DIR)/sm_io_afc_mgmt_defaults.o

core/sm_io/src/sm_io/c/modules/afc_mgmt/sm_io_afc_mgmt_core.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 LNLS (www.lnls.br)
+ * Author: Lucas Russo <[email protected]>
+ *
+ * Released according to the GNU GPL, version 3 or any later version.
+ */
+
+#include "halcs_server.h"
+/* Private headers */
+#include "sm_io_afc_mgmt_defaults.h"
+#include "sm_io_afc_mgmt_core.h"
+#include "hw/wb_afc_mgmt_regs.h"
+#include "chips_addr.h"
+
+/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
+#ifdef ASSERT_TEST
+#undef ASSERT_TEST
+#endif
+#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...)  \
+    ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_afc_mgmt_core]",               \
+            err_str, err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef ASSERT_ALLOC
+#undef ASSERT_ALLOC
+#endif
+#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...)                   \
+    ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_afc_mgmt_core]",                       \
+            smio_err_str(SMIO_ERR_ALLOC),                                       \
+            err_goto_label, /* err_core */ __VA_ARGS__)
+
+#ifdef CHECK_ERR
+#undef CHECK_ERR
+#endif
+#define CHECK_ERR(err, err_type)                                                \
+    CHECK_HAL_ERR(err, SM_IO, "[sm_io_afc_mgmt_core]",                          \
+            smio_err_str (err_type))
+
+/* AFC MGMT chip addresses */
+const uint32_t afc_mgmt_si57x_addr = 0x55;
+
+/* Creates a new instance of Device Information */
+smio_afc_mgmt_t * smio_afc_mgmt_new (smio_t *parent)
+{
+    assert (parent);
+    smio_afc_mgmt_t *self = (smio_afc_mgmt_t *) zmalloc (sizeof *self);
+    ASSERT_ALLOC(self, err_self_alloc);
+    uint32_t inst_id = smio_get_inst_id (parent);
+
+    DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:afc_mgmt_core] Si57x initializing, "
+            "addr: 0x%08X, Inst ID: %u\n", afc_mgmt_si57x_addr,
+            inst_id);
+
+    /* Create I2C protocol for Si57x chips */
+    self->smpr_i2c_si57x = smpr_i2c_new (0, afc_mgmt_si57x_addr);
+    ASSERT_ALLOC(self->smpr_i2c_si57x, err_smpr_i2c_si57x_alloc);
+
+    self->smch_si57x = smch_si57x_new (parent, AFC_MGMT_SI57X_I2C_OFFS,
+            smpr_i2c_get_ops (self->smpr_i2c_si57x), 0);
+    ASSERT_ALLOC(self->smch_si57x, err_smch_si57x_alloc);
+
+    return self;
+
+err_smch_si57x_alloc:
+    smpr_i2c_destroy (&self->smpr_i2c_si57x);
+err_smpr_i2c_si57x_alloc:
+    free (self);
+err_self_alloc:
+    return NULL;
+}
+
+/* Destroy an instance of the Device Information */
+smio_err_e smio_afc_mgmt_destroy (smio_afc_mgmt_t **self_p)
+{
+    assert (self_p);
+
+    if (*self_p) {
+        smio_afc_mgmt_t *self = *self_p;
+
+        smch_si57x_destroy (&self->smch_si57x);
+        smpr_i2c_destroy (&self->smpr_i2c_si57x);
+
+        free (self);
+        *self_p = NULL;
+    }
+
+    return SMIO_SUCCESS;
+}
+