Merge branch 'monit1-support' into devel

lnls-dig · Jun 4, 2018 · 2071d01 · 2071d01
2 parents 8ec2154 + a13e7fc
commit 2071d01
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Showing 13 changed files with 921 additions and 252 deletions.
diff --git a/core/boards/afcv3_1/src/afcv3_1/c/ddr3_map.c b/core/boards/afcv3_1/src/afcv3_1/c/ddr3_map.c
@@ -86,6 +86,16 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_FOFBPOS0_START_ADDR,
             .end_addr = DDR3_FOFBPOS0_END_ADDR
         },
+        {
+            .id = MONIT1AMP_CHAN_ID,
+            .start_addr = DDR3_MONIT1AMP0_START_ADDR,
+            .end_addr = DDR3_MONIT1AMP0_END_ADDR
+        },
+        {
+            .id = MONIT1POS_CHAN_ID,
+            .start_addr = DDR3_MONIT1POS0_START_ADDR,
+            .end_addr = DDR3_MONIT1POS0_END_ADDR
+        },
         {
             .id = MONITAMP_CHAN_ID,
             .start_addr = DDR3_MONITAMP0_START_ADDR,
@@ -96,11 +106,6 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_MONITPOS0_START_ADDR,
             .end_addr = DDR3_MONITPOS0_END_ADDR
         },
-        {
-            .id = MONIT1POS_CHAN_ID,
-            .start_addr = DDR3_MONIT1POS0_START_ADDR,
-            .end_addr = DDR3_MONIT1POS0_END_ADDR
-        }
     },
     /*** Acquisition Core 1 Channel Parameters ***/
     {
@@ -174,6 +179,16 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_FOFBPOS1_START_ADDR,
             .end_addr = DDR3_FOFBPOS1_END_ADDR
         },
+        {
+            .id = MONIT1AMP_CHAN_ID,
+            .start_addr = DDR3_MONIT1AMP1_START_ADDR,
+            .end_addr = DDR3_MONIT1AMP1_END_ADDR
+        },
+        {
+            .id = MONIT1POS_CHAN_ID,
+            .start_addr = DDR3_MONIT1POS1_START_ADDR,
+            .end_addr = DDR3_MONIT1POS1_END_ADDR
+        },
         {
             .id = MONITAMP_CHAN_ID,
             .start_addr = DDR3_MONITAMP1_START_ADDR,
@@ -184,11 +199,6 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_MONITPOS1_START_ADDR,
             .end_addr = DDR3_MONITPOS1_END_ADDR
         },
-        {
-            .id = MONIT1POS_CHAN_ID,
-            .start_addr = DDR3_MONIT1POS1_START_ADDR,
-            .end_addr = DDR3_MONIT1POS1_END_ADDR
-        },
     },
     /*** Acquisition Core 2 Channel Parameters ***/
     {
@@ -262,6 +272,16 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_FOFBPOS2_START_ADDR,
             .end_addr = DDR3_FOFBPOS2_END_ADDR
         },
+        {
+            .id = MONIT1AMP_CHAN_ID,
+            .start_addr = DDR3_MONIT1AMP2_START_ADDR,
+            .end_addr = DDR3_MONIT1AMP2_END_ADDR
+        },
+        {
+            .id = MONIT1POS_CHAN_ID,
+            .start_addr = DDR3_MONIT1POS2_START_ADDR,
+            .end_addr = DDR3_MONIT1POS2_END_ADDR
+        },
         {
             .id = MONITAMP_CHAN_ID,
             .start_addr = DDR3_MONITAMP2_START_ADDR,
@@ -272,11 +292,6 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_MONITPOS2_START_ADDR,
             .end_addr = DDR3_MONITPOS2_END_ADDR
         },
-        {
-            .id = MONIT1POS_CHAN_ID,
-            .start_addr = DDR3_MONIT1POS2_START_ADDR,
-            .end_addr = DDR3_MONIT1POS2_END_ADDR
-        },
     },
     /*** Acquisition Core 3 Channel Parameters ***/
     {
@@ -350,6 +365,16 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_FOFBPOS3_START_ADDR,
             .end_addr = DDR3_FOFBPOS3_END_ADDR
         },
+        {
+            .id = MONIT1AMP_CHAN_ID,
+            .start_addr = DDR3_MONIT1AMP3_START_ADDR,
+            .end_addr = DDR3_MONIT1AMP3_END_ADDR
+        },
+        {
+            .id = MONIT1POS_CHAN_ID,
+            .start_addr = DDR3_MONIT1POS3_START_ADDR,
+            .end_addr = DDR3_MONIT1POS3_END_ADDR
+        },
         {
             .id = MONITAMP_CHAN_ID,
             .start_addr = DDR3_MONITAMP3_START_ADDR,
@@ -360,11 +385,6 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
             .start_addr = DDR3_MONITPOS3_START_ADDR,
             .end_addr = DDR3_MONITPOS3_END_ADDR
         },
-        {
-            .id = MONIT1POS_CHAN_ID,
-            .start_addr = DDR3_MONIT1POS3_START_ADDR,
-            .end_addr = DDR3_MONIT1POS3_END_ADDR
-        },
     },
 };
 

diff --git a/core/common/include/boards/afcv3_1/acq_chan.h b/core/common/include/boards/afcv3_1/acq_chan.h
@@ -49,17 +49,20 @@
 /* FOFB POS */
 #define FOFBPOS_CHAN_ID                 (FOFBPHA_CHAN_ID + 1)
 
+/* MONIT1 AMP */
+#define MONIT1AMP_CHAN_ID               (FOFBPOS_CHAN_ID + 1)
+
+/* MONIT1 POS */
+#define MONIT1POS_CHAN_ID               (MONIT1AMP_CHAN_ID + 1)
+
 /* MONIT AMP */
-#define MONITAMP_CHAN_ID                (FOFBPOS_CHAN_ID + 1)
+#define MONITAMP_CHAN_ID                (MONIT1POS_CHAN_ID + 1)
 
 /* MONIT POS */
 #define MONITPOS_CHAN_ID                (MONITAMP_CHAN_ID + 1)
 
-/* MONIT1 POS */
-#define MONIT1POS_CHAN_ID               (MONITPOS_CHAN_ID + 1)
-
 /* End of channels placeholder */
-#define END_CHAN_ID                     (MONIT1POS_CHAN_ID + 1)
+#define END_CHAN_ID                     (MONITPOS_CHAN_ID + 1)
 
 #endif
 
diff --git a/core/common/include/boards/afcv3_1/ddr3_map.h b/core/common/include/boards/afcv3_1/ddr3_map.h
@@ -42,7 +42,7 @@
 
 #define DDR3_MIXIQ0_MEM_BOOL            DDR3_MEM_BOOL(DDR3_MIXIQ0_MEM_SIZE)
 #define DDR3_MIXIQ0_START_ADDR          (DDR3_ADCSWAP0_END_ADDR)
-#define DDR3_MIXIQ0_END_ADDR            (DDR3_MIXIQ0_START_ADDR + DDR3_MIXIQ0_MEM_SIZE*MEM_REGION_SIZE) 
+#define DDR3_MIXIQ0_END_ADDR            (DDR3_MIXIQ0_START_ADDR + DDR3_MIXIQ0_MEM_SIZE*MEM_REGION_SIZE)
 
 /* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ0)
  * Size: 1 DDR3 regions */
@@ -132,12 +132,28 @@
 #define DDR3_FOFBPOS0_START_ADDR        (DDR3_TBTPOS0_END_ADDR)
 #define DDR3_FOFBPOS0_END_ADDR          (DDR3_FOFBPOS0_START_ADDR + DDR3_FOFBPOS0_MEM_SIZE*MEM_REGION_SIZE)
 
+ /* MONIT1 1 AMP
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1AMP0_MEM_SIZE        1
+
+#define DDR3_MONIT1AMP0_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1AMP0_MEM_SIZE)
+#define DDR3_MONIT1AMP0_START_ADDR      (DDR3_FOFBPOS0_END_ADDR)
+#define DDR3_MONIT1AMP0_END_ADDR        (DDR3_MONIT1AMP0_START_ADDR + DDR3_MONIT1AMP0_MEM_SIZE*MEM_REGION_SIZE)
+
+/* MONIT1 1 POS
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1POS0_MEM_SIZE        1
+
+#define DDR3_MONIT1POS0_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS0_MEM_SIZE)
+#define DDR3_MONIT1POS0_START_ADDR      (DDR3_MONIT1AMP0_END_ADDR)
+#define DDR3_MONIT1POS0_END_ADDR        (DDR3_MONIT1POS0_START_ADDR + DDR3_MONIT1POS0_MEM_SIZE*MEM_REGION_SIZE)
+
  /* MONIT 0 AMP
  * Size: 0 DDR3 regions */
 #define DDR3_MONITAMP0_MEM_SIZE         0
 
 #define DDR3_MONITAMP0_MEM_BOOL         DDR3_MEM_BOOL(DDR3_MONITAMP0_MEM_SIZE)
-#define DDR3_MONITAMP0_START_ADDR       (DDR3_FOFBPOS0_END_ADDR)
+#define DDR3_MONITAMP0_START_ADDR       (DDR3_MONIT1POS0_END_ADDR)
 #define DDR3_MONITAMP0_END_ADDR         (DDR3_MONITAMP0_START_ADDR + DDR3_MONITAMP0_MEM_SIZE*MEM_REGION_SIZE)
 
 /* MONIT 0 POS
@@ -148,20 +164,12 @@
 #define DDR3_MONITPOS0_START_ADDR       (DDR3_MONITAMP0_END_ADDR)
 #define DDR3_MONITPOS0_END_ADDR         (DDR3_MONITPOS0_START_ADDR + DDR3_MONITPOS0_MEM_SIZE*MEM_REGION_SIZE)
 
-/* MONIT1 0 POS
- * Size: 0 DDR3 regions */
-#define DDR3_MONIT1POS0_MEM_SIZE        0
-
-#define DDR3_MONIT1POS0_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS0_MEM_SIZE)
-#define DDR3_MONIT1POS0_START_ADDR      (DDR3_MONITPOS0_END_ADDR)
-#define DDR3_MONIT1POS0_END_ADDR        (DDR3_MONIT1POS0_START_ADDR + DDR3_MONIT1POS0_MEM_SIZE*MEM_REGION_SIZE)
-
 /* End 0 Dummy region
  * Size: 0 DDR3 regions */
 #define DDR3_DUMMY_END0_MEM_SIZE        0
 
 #define DDR3_DUMMY_END0_MEM_BOOL        DDR3_MEM_BOOL(DDR3_DUMMY_END0_MEM_SIZE)
-#define DDR3_DUMMY_END0_START_ADDR      (DDR3_MONIT1POS0_END_ADDR)
+#define DDR3_DUMMY_END0_START_ADDR      (DDR3_MONITAMP0_END_ADDR)
 #define DDR3_DUMMY_END0_END_ADDR        (DDR3_DUMMY_END0_START_ADDR + DDR3_DUMMY_END0_MEM_SIZE*MEM_REGION_SIZE)
 
 /************************ Acquistion 1 Channel Parameters **************/
@@ -278,12 +286,28 @@
 #define DDR3_FOFBPOS1_START_ADDR        (DDR3_TBTPOS1_END_ADDR)
 #define DDR3_FOFBPOS1_END_ADDR          (DDR3_FOFBPOS1_START_ADDR + DDR3_FOFBPOS1_MEM_SIZE*MEM_REGION_SIZE)
 
+ /* MONIT1 1 AMP
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1AMP1_MEM_SIZE        1
+
+#define DDR3_MONIT1AMP1_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1AMP1_MEM_SIZE)
+#define DDR3_MONIT1AMP1_START_ADDR      (DDR3_FOFBPOS1_END_ADDR)
+#define DDR3_MONIT1AMP1_END_ADDR        (DDR3_MONIT1AMP1_START_ADDR + DDR3_MONIT1AMP1_MEM_SIZE*MEM_REGION_SIZE)
+
+/* MONIT1 1 POS
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1POS1_MEM_SIZE        1
+
+#define DDR3_MONIT1POS1_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS1_MEM_SIZE)
+#define DDR3_MONIT1POS1_START_ADDR      (DDR3_MONIT1AMP1_END_ADDR)
+#define DDR3_MONIT1POS1_END_ADDR        (DDR3_MONIT1POS1_START_ADDR + DDR3_MONIT1POS1_MEM_SIZE*MEM_REGION_SIZE)
+
  /* MONIT 1 AMP
  * Size: 1 DDR3 regions */
 #define DDR3_MONITAMP1_MEM_SIZE         0
 
 #define DDR3_MONITAMP1_MEM_BOOL         DDR3_MEM_BOOL(DDR3_MONITAMP1_MEM_SIZE)
-#define DDR3_MONITAMP1_START_ADDR       (DDR3_FOFBPOS1_END_ADDR)
+#define DDR3_MONITAMP1_START_ADDR       (DDR3_MONIT1POS1_END_ADDR)
 #define DDR3_MONITAMP1_END_ADDR         (DDR3_MONITAMP1_START_ADDR + DDR3_MONITAMP1_MEM_SIZE*MEM_REGION_SIZE)
 
 /* MONIT 1 POS
@@ -294,20 +318,12 @@
 #define DDR3_MONITPOS1_START_ADDR       (DDR3_MONITAMP1_END_ADDR)
 #define DDR3_MONITPOS1_END_ADDR         (DDR3_MONITPOS1_START_ADDR + DDR3_MONITPOS1_MEM_SIZE*MEM_REGION_SIZE)
 
-/* MONIT1 1 POS
- * Size: 1 DDR3 regions */
-#define DDR3_MONIT1POS1_MEM_SIZE        0
-
-#define DDR3_MONIT1POS1_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS1_MEM_SIZE)
-#define DDR3_MONIT1POS1_START_ADDR      (DDR3_MONITPOS1_END_ADDR)
-#define DDR3_MONIT1POS1_END_ADDR        (DDR3_MONIT1POS1_START_ADDR + DDR3_MONIT1POS1_MEM_SIZE*MEM_REGION_SIZE)
-
 /* End 1 Dummy region
  * Size: 0 DDR3 regions */
 #define DDR3_DUMMY_END1_MEM_SIZE        0
 
 #define DDR3_DUMMY_END1_MEM_BOOL        DDR3_MEM_BOOL(DDR3_DUMMY_END1_MEM_SIZE)
-#define DDR3_DUMMY_END1_START_ADDR      (DDR3_MONIT1POS1_END_ADDR)
+#define DDR3_DUMMY_END1_START_ADDR      (DDR3_MONITPOS1_END_ADDR)
 #define DDR3_DUMMY_END1_END_ADDR        (DDR3_DUMMY_END1_START_ADDR + DDR3_DUMMY_END1_MEM_SIZE*MEM_REGION_SIZE)
 
 /************************ Acquistion 2 Channel Parameters **************/
@@ -424,6 +440,22 @@
 #define DDR3_FOFBPOS2_START_ADDR        (DDR3_DUMMY_END1_END_ADDR)
 #define DDR3_FOFBPOS2_END_ADDR          (DDR3_FOFBPOS2_START_ADDR + DDR3_FOFBPOS2_MEM_SIZE*MEM_REGION_SIZE)
 
+ /* MONIT1 1 AMP
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1AMP2_MEM_SIZE        0
+
+#define DDR3_MONIT1AMP2_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1AMP2_MEM_SIZE)
+#define DDR3_MONIT1AMP2_START_ADDR      (DDR3_DUMMY_END1_END_ADDR)
+#define DDR3_MONIT1AMP2_END_ADDR        (DDR3_MONIT1AMP2_START_ADDR + DDR3_MONIT1AMP2_MEM_SIZE*MEM_REGION_SIZE)
+
+/* MONIT1 1 POS
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1POS2_MEM_SIZE        0
+
+#define DDR3_MONIT1POS2_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS2_MEM_SIZE)
+#define DDR3_MONIT1POS2_START_ADDR      (DDR3_DUMMY_END1_END_ADDR)
+#define DDR3_MONIT1POS2_END_ADDR        (DDR3_MONIT1POS2_START_ADDR + DDR3_MONIT1POS2_MEM_SIZE*MEM_REGION_SIZE)
+
  /* MONIT 1 AMP
  * Size: 1 DDR3 regions */
 #define DDR3_MONITAMP2_MEM_SIZE         0
@@ -440,20 +472,12 @@
 #define DDR3_MONITPOS2_START_ADDR       (DDR3_DUMMY_END1_END_ADDR)
 #define DDR3_MONITPOS2_END_ADDR         (DDR3_MONITPOS2_START_ADDR + DDR3_MONITPOS2_MEM_SIZE*MEM_REGION_SIZE)
 
-/* MONIT2 1 POS
- * Size: 1 DDR3 regions */
-#define DDR3_MONIT1POS2_MEM_SIZE        0
-
-#define DDR3_MONIT1POS2_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS2_MEM_SIZE)
-#define DDR3_MONIT1POS2_START_ADDR      (DDR3_DUMMY_END1_END_ADDR)
-#define DDR3_MONIT1POS2_END_ADDR        (DDR3_MONIT1POS2_START_ADDR + DDR3_MONIT1POS2_MEM_SIZE*MEM_REGION_SIZE)
-
 /* End 2 Dummy region. Default this to the maximum memory area size.
  * Size: 2 DDR3 regions */
 #define DDR3_DUMMY_END2_MEM_SIZE        2
 
 #define DDR3_DUMMY_END2_MEM_BOOL        DDR3_MEM_BOOL(DDR3_DUMMY_END2_MEM_SIZE)
-#define DDR3_DUMMY_END2_START_ADDR      (DDR3_MONIT1POS2_END_ADDR)
+#define DDR3_DUMMY_END2_START_ADDR      (DDR3_MONITPOS2_END_ADDR)
 #define DDR3_DUMMY_END2_END_ADDR        (DDR3_DUMMY_END2_START_ADDR + DDR3_DUMMY_END2_MEM_SIZE*MEM_REGION_SIZE)
 
 /************************ Acquistion 3 Channel Parameters **************/
@@ -570,6 +594,22 @@
 #define DDR3_FOFBPOS3_START_ADDR        (DDR3_DUMMY_END2_END_ADDR)
 #define DDR3_FOFBPOS3_END_ADDR          (DDR3_FOFBPOS3_START_ADDR + DDR3_FOFBPOS3_MEM_SIZE*MEM_REGION_SIZE)
 
+ /* MONIT1 1 AMP
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1AMP3_MEM_SIZE        0
+
+#define DDR3_MONIT1AMP3_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1AMP3_MEM_SIZE)
+#define DDR3_MONIT1AMP3_START_ADDR      (DDR3_DUMMY_END2_END_ADDR)
+#define DDR3_MONIT1AMP3_END_ADDR        (DDR3_MONIT1AMP3_START_ADDR + DDR3_MONIT1AMP3_MEM_SIZE*MEM_REGION_SIZE)
+
+/* MONIT1 1 POS
+ * Size: 1 DDR3 regions */
+#define DDR3_MONIT1POS3_MEM_SIZE        0
+
+#define DDR3_MONIT1POS3_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS3_MEM_SIZE)
+#define DDR3_MONIT1POS3_START_ADDR      (DDR3_DUMMY_END2_END_ADDR)
+#define DDR3_MONIT1POS3_END_ADDR        (DDR3_MONIT1POS3_START_ADDR + DDR3_MONIT1POS3_MEM_SIZE*MEM_REGION_SIZE)
+
  /* MONIT 1 AMP
  * Size: 1 DDR3 regions */
 #define DDR3_MONITAMP3_MEM_SIZE         0
@@ -586,14 +626,6 @@
 #define DDR3_MONITPOS3_START_ADDR       (DDR3_DUMMY_END2_END_ADDR)
 #define DDR3_MONITPOS3_END_ADDR         (DDR3_MONITPOS3_START_ADDR + DDR3_MONITPOS3_MEM_SIZE*MEM_REGION_SIZE)
 
-/* MONIT2 1 POS
- * Size: 1 DDR3 regions */
-#define DDR3_MONIT1POS3_MEM_SIZE        0
-
-#define DDR3_MONIT1POS3_MEM_BOOL        DDR3_MEM_BOOL(DDR3_MONIT1POS3_MEM_SIZE)
-#define DDR3_MONIT1POS3_START_ADDR      (DDR3_DUMMY_END2_END_ADDR)
-#define DDR3_MONIT1POS3_END_ADDR        (DDR3_MONIT1POS3_START_ADDR + DDR3_MONIT1POS3_MEM_SIZE*MEM_REGION_SIZE)
-
 /* End 3 Dummy region. Default this to the maximum memory area size.
  * Size: 2 DDR3 regions */
 #define DDR3_DUMMY_END3_MEM_SIZE        2