Merge branch 'devel'

core/boards/common/src/common/c/chips_addr_common.c

@@ -7,7 +7,3 @@
 
 #include "halcs_server.h"
 
-/* FMC ACTIVE CLOCK chip addresses */
-const uint32_t fmc_active_clk_si571_addr = 0x49;
-const uint32_t fmc_active_clk_ad9510_addr = 0x01;
-

core/common/include/chips/si57x_regs.h

@@ -189,6 +189,7 @@
 #define SI57X_REG_START                                     SI57X_REG_HS_N1
 
 #define SI57X_NUM_DIV_REGS                                  6
+#define SI57X_NUM_RFREQ_REGS                                5
 
 #endif
 

core/common/include/chips/sm_ch_si57x_defaults.h

@@ -15,6 +15,7 @@
 #define SMCH_SI57X_DFLT_HSDIV                   0
 #define SMCH_SI57X_DFLT_RFREQ                   0ULL
 #define SMCH_SI57X_DFLT_FREQUENCY               SI57X_FOUT_FACTORY_DFLT
+#define SMCH_SI57X_DFLT_FACTORY                 SI57X_FOUT_FACTORY_DFLT
 
 #endif
 

core/common/include/chips_addr_common.h

@@ -12,9 +12,6 @@
 extern "C" {
 #endif
 
-extern const uint32_t fmc_active_clk_si571_addr;
-extern const uint32_t fmc_active_clk_ad9510_addr;
-
 #ifdef __cplusplus
 }
 #endif

core/common/include/hal_stddef.h

@@ -36,6 +36,36 @@
 
 #define ARRAY_SIZE(ARRAY) (sizeof(ARRAY)/sizeof((ARRAY)[0]))
 
+/*
+ * Divide positive or negative dividend by positive or negative divisor
+ * and round to closest integer. Result is undefined for negative
+ * divisors if he dividend variable type is unsigned and for negative
+ * dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)(			\
+{							\
+	typeof(x) __x = x;				\
+	typeof(divisor) __d = divisor;			\
+	(((typeof(x))-1) > 0 ||				\
+	 ((typeof(divisor))-1) > 0 ||			\
+	 (((__x) > 0) == ((__d) > 0))) ?		\
+		(((__x) + ((__d) / 2)) / (__d)) :	\
+		(((__x) - ((__d) / 2)) / (__d));	\
+}							\
+)
+/*
+ * Same as above but for u64 dividends. divisor must be a 32-bit
+ * number.
+ */
+#define DIV_ROUND_CLOSEST_ULL(x, divisor)(		\
+{							\
+	typeof(divisor) __d = divisor;			\
+	unsigned long long _tmp = (x) + (__d) / 2;	\
+	do_div(_tmp, __d);				\
+	_tmp;						\
+}							\
+)
+
 /* Signal handler function pointer */
 typedef void (*sig_handler_fp)(int sig, siginfo_t *siginfo, void *context);
 /* Wait child handler function pointer */

core/common/include/hw/wb_acq_core_regs.h

@@ -3,15 +3,15 @@
 
   * File           : wb_acq_core_regs.h
   * Author         : auto-generated by wbgen2 from acq_core.wb
-  * Created        : Fri Mar 24 14:49:10 2017
+  * Created        : Tue Aug 15 08:46:29 2017
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
     DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
 
 */
 
-/* This file has been modified! */
+/* This file has been modified to include the ML605 fix! */
 
 #ifndef __WBGEN2_REGDEFS_ACQ_CORE_WB
 #define __WBGEN2_REGDEFS_ACQ_CORE_WB
@@ -192,10 +192,22 @@
 #define ACQ_CORE_ACQ_CHAN_CTL_DTRIG_WHICH_R(reg) WBGEN2_GEN_READ(reg, 8, 5)
 
 /* definitions for field: Reserved1 in reg: Acquisition channel control */
-#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_MASK  WBGEN2_GEN_MASK(13, 19)
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_MASK  WBGEN2_GEN_MASK(13, 3)
 #define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_SHIFT 13
-#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 13, 19)
-#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 13, 19)
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 13, 3)
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 13, 3)
+
+/* definitions for field: Number of acquisition channels in reg: Acquisition channel control */
+#define ACQ_CORE_ACQ_CHAN_CTL_NUM_CHAN_MASK   WBGEN2_GEN_MASK(16, 5)
+#define ACQ_CORE_ACQ_CHAN_CTL_NUM_CHAN_SHIFT  16
+#define ACQ_CORE_ACQ_CHAN_CTL_NUM_CHAN_W(value) WBGEN2_GEN_WRITE(value, 16, 5)
+#define ACQ_CORE_ACQ_CHAN_CTL_NUM_CHAN_R(reg) WBGEN2_GEN_READ(reg, 16, 5)
+
+/* definitions for field: Reserved2 in reg: Acquisition channel control */
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED2_MASK  WBGEN2_GEN_MASK(21, 11)
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED2_SHIFT 21
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED2_W(value) WBGEN2_GEN_WRITE(value, 21, 11)
+#define ACQ_CORE_ACQ_CHAN_CTL_RESERVED2_R(reg) WBGEN2_GEN_READ(reg, 21, 11)
 
 /* definitions for register: Channel 0 Description */
 

core/common/include/sm_ch_si57x.h

@@ -40,6 +40,10 @@ smch_err_e smch_si57x_get_defaults (smch_si57x_t *self, double fout);
 smch_err_e smch_si57x_set_freq (smch_si57x_t *self, double *freq);
 /* Get current frequency */
 smch_err_e smch_si57x_get_freq (smch_si57x_t *self, double *freq);
+/* Set startup frequency */
+smch_err_e smch_si57x_set_fstartup (smch_si57x_t *self, double fstartup);
+/* Get startup frequency */
+double smch_si57x_get_fstartup (smch_si57x_t *self);
 
 #ifdef __cplusplus
 }

core/sm_io/include/sm_io_fmc_active_clk_codes.h

@@ -49,8 +49,10 @@
 #define FMC_ACTIVE_CLK_OPCODE_RST_SWAP                     17
 #define FMC_ACTIVE_CLK_NAME_RST_SWAP                       "fmc_active_clk_rst_swap"
 #define FMC_ACTIVE_CLK_OPCODE_AD9510_DATA                  18
-#define FMC_ACTIVE_CLK_NAME_AD9510_DATA                    "fmc130m_4ch_ad9510_data"
-#define FMC_ACTIVE_CLK_OPCODE_END                          19
+#define FMC_ACTIVE_CLK_NAME_AD9510_DATA                    "fmc_active_clk_ad9510_data"
+#define FMC_ACTIVE_CLK_OPCODE_SI571_FSTARTUP               19
+#define FMC_ACTIVE_CLK_NAME_SI571_FSTARTUP                 "fmc_active_clk_si571_fstartup"
+#define FMC_ACTIVE_CLK_OPCODE_END                          20
 
 /* Messaging Reply OPCODES */
 #define FMC_ACTIVE_CLK_REPLY_TYPE                          uint32_t