ADC Reset #44
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ADC Reset #44
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We name the file the same as the uhal module, but shorten it to fmc250m everywhere else.
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| # combining state with fmc_adc_common | ||
| record(bi,"$(P)$(R)ClksLocked-Mon"){ | ||
| field(DESC, "state of PLL and MMCM clocks") |
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We implement this record in fmc_active_clk because the MMCM clock always exists, but the AD9510 PLL clock is only available if the fmc_active_clk module is present.
This means such PV won't abstract away the existence of two states, right? If fmc_active_clk module is not present, users will have to rely on MMCMLocked-Mon to know if it is locked.
I assume this such situation will happen for different boards, so we don't bother about it. Is that it?
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Commit message updated to address this.
Looking at only the PLL or MMCM clock status is not enough to fully represent the status of the BPM clock chain. We implement this record in fmc_active_clk because the MMCM clock always exists, but the AD9510 PLL clock is only available if the fmc_active_clk module is present. All of our boards have an active clock, so we don't take boards without it into account for now.
Using this module, we implement a feature to automatically reset the relevant devices (ISLA216p ADCs and FPGA MMCM) when there is a transition from the device clocks being "not_locked" to "locked". This situation can happen during board startup, when the ADCs receive no clock signal, and can only be properly reset after they start receiving it; and during operation, if the clock reference is lost, making it necessary to reset the ADC and MMCM in order to guarantee stable behavior from them.
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